Rainbow-electronics MAX1329 Bedienungsanleitung PDF herunterladen (Seite 37)

MAX1329/MAX1330

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,

Reference, Voltage Monitors, and Temp Sensor

______________________________________________________________________________________ 37

Once configured, autoconvert mode initiates with one

ADC Convert command. Conversions continue at the

rate selected by the ADC Autoconvert bits (see Table 4)

until disabled by writing to the ADC Control register. The

Autoconvert mode can run only in the normal or fast

power-down modes. The autoconvert function must be

disabled to use burst mode or DPIO CONVST mode.

When writing to the ADC Control register in fast power-

down mode with autoconvert disabled, acquisition

begins on the 1st rising ADC clock edge after CS tran-

sitions high, and ends after the programmed number of

clock cycles. The conversion completes a minimum 14

clock cycles after acquisition ends. When autoconvert

is enabled, an additional three ADC clock cycles are

added prior to acquisition to allow the ADC to wake up.

See Figures 19 and 20 for timing diagrams.

1M3M2M1

G1 G0 BIP

SCLK

DIN

123 67845

TRACK

CONVERT

ADC MODE

ADCDONE**

123 678910111213181945

CLKIO

PD*

*PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN.

**ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER.

X = DON'T CARE.

Figure 20. Write Command to Start ADC Normal or Fast Power-Down, with Autoconvert Enabled and Conversions Clocked by CLKIO

(OSCE = 0, ADDIV<1:0> = 00, CLKIO<1:0> = 11)

CLKIO

ADC MODE

DPIO (CONVST)

CONVERT

EDGE TRIGGERED

TRACKTRACK

1 2 3 4 5 6 7 8 9 1011121314151617181920 212223

PD*

ADCDONE**

*PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN.

**ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER.

ADDIV = 00.

Figure 21. DPIO-Controlled ADC Conversion Start

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 77 78

MAX1329/MAX1330 1

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