MAX4885
Complete VGA 1:2 or 2:1 Multiplexer
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2:1 Multiplexer
In 2:1 mode, HSYNC and VSYNC buffers are disabled,
allowing bidirectional signaling. The DDC multiplexer
provides level shifting by clamping signals to a diode
drop less than V
CL
(see the Typical Operating Circuit).
Connect V
CL
to V+ to disable voltage clamping for
DDC signals.
Power-Supply Decoupling
Bypass each V+ pin and V
CL
to ground with a 0.1µF or
larger ceramic capacitor as close to the device as pos-
sible.
PC Board Layout
High-speed switches such as the MAX4885 require
proper PC board layout for optimum performance.
Ensure that impedance-controlled PC board traces for
high-speed signals are matched in length and as short
as possible. Connect the exposed pad to a solid
ground plane.
Chip Information
PROCESS: BiCMOS
CONNECT EXPOSED PAD TO GND
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