
MAX4885
Complete VGA 1:2 or 2:1 Multiplexer
_______________________________________________________________________________________ 7
t
r
< 5ns
t
f
< 5ns
50%
0V
LOGIC
INPUT
R
L
R0, G0, B0
GND
SEL
C
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
V
OUT
= V
N_ (
R
L
)
R
L
+ R
ON
V
N_
V+
t
OFF
0V
R1, G1, B1
R2, G2, B2
0.9 x V
0UT
0.9 x V
OUT
t
ON
V
OUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
V+
C
L
V+
V
OUT
MAX4885
50%
Timing Circuits/Timing Diagrams
INPUT
OUTPUT
V
OH
t
PHL
t
PLH
t
SKEW
= | t
PLH
- t
PHL
|
t
PD
= MAX (t
PLH
, t
PHL
)
1V
50%
0V
50%
0.9V
50%
50%
0V
R
S
= R
L
= 50Ω
C
L
= 10pF
V
GEN
GND
C
L
V
OUT
V+
V
OUT
IN
OFF
ON
OFF
∆V
OUT
Q = (∆V
OUT
)(C
L
)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF
ON
OFF
IN
V
IL
TO V
IH
V+
R
GEN
SEL
MAX4885
R0, G0, B0
R1, G1, B1
R2, G2, B2
Figure 1. Switching Time
Figure 2. Propagation Delay and Skew Waveforms
Figure 3. Charge Injection
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