MAX5122/MAX5123
+5V/+3V, 12-Bit, Serial, Force/Sense DACs
with 10ppm/°C Internal Reference
12 ______________________________________________________________________________________
Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables shutdown
when low. When in shutdown mode, a high-to-low tran-
sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
Power-Down Input (PD)
Pulling PD high places the MAX5122/MAX5123 in shut-
down. Pulling PD low will not return the MAX5122/
MAX5123 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the ser-
ial interface are required to exit power-down mode.
Serial-Interface Configuration
(SPI/QSPI/MICROWIRE/PIC16/PIC17)
The MAX5122/MAX5123 3-wire serial interface is com-
patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2-
byte-long serial input word contains three control bits,
12 data bits in MSB-first format, and one sub-bit, which
is always zero (Table 2).
The MAX5122/MAX5123’s digital inputs are double
buffered, which allows the user to:
• Load the input register without updating the DAC
register,
• Update the DAC register with data from the input
register,
• Update the input and DAC registers concurrently.
Load input register; DAC register unchanged.12-Bit DAC Data0 0
0
1
0
Update DAC register from input register; exit shutdown.XXXXXXXXXXXX0 1
1
1
0 Simultaneously load input and DAC registers; exit shutdown.12-Bit DAC Data0
UPO goes low (default).XXXXXXXXXXXX1 0
0
0
1
Mode 1; DOUT clocked out on SCLK’s rising edge.1XXXXXXXXXXX1 1
1
1
0 UPO goes high.XXXXXXXXXXXX1
No operation.XXXXXXXXXXXX0
Shutdown DAC (provided PDL = 1).
XXXXXXXXXXXX1
Mode 0; DOUT clocked out on SCLK’s falling edge (default).00XXXXXXXXXX1 1 1
C1 C0C2
FUNCTION
D11 ............... D0
Table 1. Serial-Interface Programming Commands
X = Don’t care
*
S0 is a sub-bit and always zero.
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