Rainbow-electronics MAX5157 Bedienungsanleitung PDF herunterladen (Seite 3)

MAX5156/MAX5157

Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

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ELECTRICAL CHARACTERISTICS—MAX5156 (continued)

= +5V ±10%, V

REFA

= V

REFB

= 2.5V, R

= 10kΩ, C

= 100pF, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

Note 1: Accuracy is specified from code 10 to code 4095.

Note 2: Accuracy is better than 1LSB for V

OUT

greater than 6mV and less than V

- 50mV. Guaranteed by PSRR test at the end points.

Note 3: Digital inputs are set to either V

or DGND, code = 0000 hex, R

= ∞.

Note 4: SCLK minimum clock period includes rise and fall times.

CS = V

, f

DIN

= 100kHz, V

SCLK

= 5Vp-p

SOURCE

= 2mA

Rail-to-rail (Note 2)

To 1/2LSB of full-scale, V

STEP

= 2.5V

SINK

= 2mA

CONDITIONS

nV-s5Digital Crosstalk

nV-s5Digital Feedthrough

µs25Time Required to Exit Shutdown

µA0 ±0.1I

Current into FBA or FBB

- 0.5V

Output High Voltage

V0 to V

Output Voltage Swing

µs15Output Settling Time

V0.13 0.40V

Output Low Voltage

V/µs0.75SRVoltage Output Slew Rate

UNITSMIN TYP MAXSYMBOLPARAMETER

(Note 4)

(Note 3)

ns40t

SCLK Pulse Width Low

ns40t

SCLK Pulse Width High

ns100t

SCLK Clock Period

µA0 ±1Reference Current in Shutdown

µA2 10I

DD(SHDN)

Power-Supply Current in

Shutdown

mA0.5 0.65I

Power-Supply Current

V4.5 5.5V

Positive Supply Voltage

ns40t

DIN Setup Time

ns0t

CHS

SCLK Rise to CS Rise Hold Time

ns40t

CSS

CS Fall to SCLK Rise Setup Time

LOAD

= 200pF

LOAD

= 200pF

ns80t

DO2

SCLK Fall to DOUT Valid

Propagation Delay

ns80t

DO1

SCLK Rise to DOUT Valid

Propagation Delay

ns0t

DIN Hold Time

ns100t

CSW

CS Pulse Width High

ns40t

CS1

CS Rise to SCLK Rise Hold

ns10t

CS0

SCLK Rise to CS Fall Delay

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS

1 2 3 4 5 6 7 8 ... 15 16

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