I
2
C Compatibility
The MAX5360/MAX5361/MAX5362 are compatible with
existing I
2
C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I
2
C application. The communication protocol
supports the standard I
2
C 8-bit communications. The
general call address is ignored, and CBUS formats are
not supported. The MAX5360/MAX5361/MAX5362
address is compatible with the 7-bit I
2
C addressing
protocol only. No 10-bit formats are supported.
RESTART protocol is supported, but an immediate
STOP condition is necessary to update the DAC.
Applications Information
Digital Inputs and Interface Logic
The serial 2-wire interface has logic levels defined as
V
OL
= 0.3
✕
V
DD
and V
OH
= 0.7
✕
V
DD
. All of the inputs
include Schmitt-trigger buffers to accept slow-transition
interfaces. This means that optocouplers can interface
directly to the MAX5360/MAX5361/MAX5362 without
additional external logic. The digital inputs are compati-
ble with CMOS logic levels and must not be driven with
voltages higher than V
DD
.
Power-Supply Bypassing and Layout
Careful PC board layout is important for best system
performance. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Ensure that
the ground return from GND to the supply ground is
short and low impedance; a ground plane is recom-
mended. Bypass V
DD
with a 0.1µF to ground as close
as possible to the device. If the supply is excessively
noisy, connect a 10Ω resistor in series with the supply
and V
DD
, and add additional capacitance
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
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