Rainbow-electronics T89C51RD2 Bedienungsanleitung

Rev. F - 15 February, 2001 1T89C51RD20 to 40MHz Flash Programmable 8-bit Microcontroller1. DescriptionATMEL Wireless and Microcontrollers T89C51RD2 is

Rev. F - 15 February, 2001 10T89C51RD26. Enhanced FeaturesIn comparison to the original 80C52, the T89C51RD2 implements some new features, which are:

11 Rev. F - 15 February, 2001T89C51RD2Figure 2. Mode Switching WaveformsThe X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock

Rev. F - 15 February, 2001 12T89C51RD2Reset Value = X000 0000bNot bit addressable1 T0X2Timer0 clock (This control bit is validated when the CPU clock

Rev. F - 15 February, 2001 13T89C51RD26.2. Dual Data Pointer Register DdptrThe additional data pointer can be used to speed up code execution and redu

14 Rev. F - 15 February, 2001T89C51RD2; Block move using dual data pointers; Modifies DPTR0, DPTR1, A and PSW; note: DPS exits opposite of entry state

Rev. F - 15 February, 2001 15T89C51RD26.3. Expanded RAM (XRAM)The T89C51RD2 provide additional Bytes of random access memory (RAM) space for increased

16 Rev. F - 15 February, 2001T89C51RD2• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions.This part

Rev. F - 15 February, 2001 17T89C51RD26.4. Timer 2The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52.It is a 16-bit timer/counte

18 Rev. F - 15 February, 2001T89C51RD2Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)6.4.2. Programmable Clock-OutputIn the clock-out mode, tim

Rev. F - 15 February, 2001 19T89C51RD2It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configurat

2 Rev. F - 15 February, 2001T89C51RD2• Power supply:- M version: Commercial and industrial4.5V to 5.5V : 40MHz X1 Mode, 20MHz X2 Mode3V to 5.5V : 33MH

20 Rev. F - 15 February, 2001T89C51RD2Table 5. T2CON RegisterT2CON - Timer 2 Control Register (C8h)Reset Value = 0000 0000bBit addressable7 6 5 4 3 2

Rev. F - 15 February, 2001 21T89C51RD2Table 6. T2MOD RegisterT2MOD - Timer 2 Mode Control Register (C9h)Reset Value = XXXX XX00bNot bit addressable7 6

Rev. F - 15 February, 2001 22T89C51RD26.5. Programmable Counter Array PCAThe PCA provides more timing capabilities with less CPU intervention than the

23 Rev. F - 15 February, 2001T89C51RD2Figure 7. PCA Timer/CounterTable 7. CMOD: PCA Counter Mode RegisterThe CMOD SFR includes three additional bits a

Rev. F - 15 February, 2001 24T89C51RD2• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be setwhen th

25 Rev. F - 15 February, 2001T89C51RD2Figure 8. PCA Interrupt SystemPCA Modules: each one of the five compare/capture modules has six possible functio

Rev. F - 15 February, 2001 26T89C51RD2Table 9. CCAPMn: PCA Modules Compare/Capture Control RegistersTable 10. PCA Module Modes (CCAPMn Registers)There

27 Rev. F - 15 February, 2001T89C51RD2Table 11. CCAPnH: PCA Modules Capture/Compare Registers HighTable 12. CCAPnL: PCA Modules Capture/Compare Regist

Rev. F - 15 February, 2001 28T89C51RD2Figure 9. PCA Capture Mode6.5.2. 16-bit Software Timer / Compare ModeThe PCA modules can be used as software tim

29 Rev. F - 15 February, 2001T89C51RD2Figure 10. PCA Compare Mode and PCA Watchdog TimerBefore enabling ECOM bit, CCAPnL and CCAPnH should be set with

Rev. F - 15 February, 2001 3T89C51RD24. SFR MappingThe Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories:• C51 cor

Rev. F - 15 February, 2001 30T89C51RD2Figure 11. PCA High Speed Output ModeBefore enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero v

31 Rev. F - 15 February, 2001T89C51RD2SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows fromF

Rev. F - 15 February, 2001 32T89C51RD26.6. Serial I/O PortThe serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52.It

33 Rev. F - 15 February, 2001T89C51RD2Figure 15. UART Timings in Modes 2 and 36.6.2. Automatic Address RecognitionThe automatic address recognition f

Rev. F - 15 February, 2001 34T89C51RD2The SADEN byte is selected so that each slave may be addressed separately.For slave A, bit 0 (the LSB) is a don’

35 Rev. F - 15 February, 2001T89C51RD2SCON - Serial Control Register (98h)Reset Value = 0000 0000bBit addressable7 6 5 4 3 2 1 0FE/SM0 SM1 SM2 REN TB8

Rev. F - 15 February, 2001 36T89C51RD2Table 16. PCON RegisterPCON - Power Control Register (87h)Reset Value = 00X1 0000bNot bit addressablePower-off f

Rev. F - 15 February, 2001 37T89C51RD26.7. Interrupt SystemThe T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1),

38 Rev. F - 15 February, 2001T89C51RD2Table 17. Priority Level Bit ValuesA low-priority interrupt can be interrupted by a high priority interrupt, but

Rev. F - 15 February, 2001 39T89C51RD2Table 19. IP RegisterIP - Interrupt Priority Register (B8h)Reset Value = X000 0000bBit addressable7 6 5 4 3 2 1

4 Rev. F - 15 February, 2001T89C51RD2reserved

40 Rev. F - 15 February, 2001T89C51RD2Table 20. IPH RegisterIPH - Interrupt Priority High Register (B7h)Reset Value = X000 0000bNot bit addressable7 6

Rev. F - 15 February, 2001 41T89C51RD26.8. Idle modeAn instruction that sets PCON.0 causes that to be the last instruction executed before going into

42 Rev. F - 15 February, 2001T89C51RD2This table shows the state of ports during idle and power-down modes.* Port 0 can force a 0 level. A "one&q

Rev. F - 15 February, 2001 43T89C51RD26.10. Hardware Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be subject

44 Rev. F - 15 February, 2001T89C51RD2Table 22. WDTPRG RegisterWDTPRG Address (0A7h)Reset value XXXX X0006.10.2. WDT during Power Down and IdleIn Powe

Rev. F - 15 February, 2001 45T89C51RD26.11. ONCE(TM) Mode (ON Chip Emulation)The ONCE mode facilitates testing and debugging of systems using T89C51RD

Rev. F - 15 February, 2001 46T89C51RD26.12. Reduced EMI ModeThe ALE signal is used to demultiplex address and data buses on port 0 when used with exte

Rev. F - 15 February, 2001 47T89C51RD27. EEPROM data memory7.1. General descriptionThe EEPROM memory block contains 2048 bytes and is organized in 32

48 Rev. F - 15 February, 2001T89C51RD2Example : ... ; DPTR = EEPROM data pointer, A = Data to write Wait : MOV A,EECON

Rev. F - 15 February, 2001 49T89C51RD2Table 26. EETIM RegisterEETIM (S:0D3h)EEPROM timing Control RegisterReset Value= 0000 0000b76543210EETIMBit Numb

Rev. F - 15 February, 2001 5T89C51RD25. Pin ConfigurationP1.7CEX4 P1.4/CEX1RSTP3.0/RxDP3.1/TxD P1.3CEX0 1P1.5/CEX2P1.6/CEX3P3.2/INT0P3.3/INT1P3.4/T0P3

Rev. F - 15 February, 2001 50T89C51RD28. FLASH EEprom Memory8.1. General descriptionThe FLASH memory increases EPROM and ROM functionality with in-cir

51 Rev. F - 15 February, 2001T89C51RD2The bootloader and the In Application Programming (IAP) routines are located in the last kilobyte of the FLASH,l

Rev. F - 15 February, 2001 52T89C51RD28.4.2.1. Boot Loader Lock Bit (BLLB)One bit of the HSB is used to secure by hardware the internal boot loader se

53 Rev. F - 15 February, 2001T89C51RD2Table 28. Program Lock bitsU: unprogrammed or "one" level.P: programmed or "zero" level.X:do

Rev. F - 15 February, 2001 54T89C51RD2They are several software registers described in Table 29Table 29. Default valuesAfter programming the part by I

55 Rev. F - 15 February, 2001T89C51RD2Table 31. Program Lock bits of the SSBU: unprogrammed or "one" level.P: programmed or "zero"

Rev. F - 15 February, 2001 56T89C51RD2erase block, program byte or page, verify byte or page, program security lock bit, etc. The Boot FLASH can beloc

57 Rev. F - 15 February, 2001T89C51RD2Boot process summaryThe boot process is summarized on the following flowchart:Figure 21. Boot process flowchartC

Rev. F - 15 February, 2001 58T89C51RD28.7. In-System Programming (ISP)The In-System Programming (ISP) is performed without removing the microcontrolle

59 Rev. F - 15 February, 2001T89C51RD2Table 32. Intel-Hex Records Used by In-System ProgrammingRECORD TYPE COMMAND/DATA FUNCTION00Data Record:nnaaaa00

6 Rev. F - 15 February, 2001T89C51RD21210151413111617181920212223242526P5.5P0.3/AD3P0.2/AD2P5.6P0.1/AD1P0.0/AD0P5.7VCCVSS1P1.0/T2P4.0P1.1/T2EXP1.2/ECI

Rev. F - 15 February, 2001 60T89C51RD203Miscellaneous Write Functions:nnxxxx03ffssddccWhere:nn = number of bytes (hex) in recordxxxx = required field,

61 Rev. F - 15 February, 2001T89C51RD28.8. In-Application Programming MethodSeveral Application Program Interface (API) calls are available for use by

Rev. F - 15 February, 2001 62T89C51RD2PROGRAM DATA PAGEInput Parameters:R0 = osc freq (integer Not required)R1 = 09hDPTR0 = address of the first byte

63 Rev. F - 15 February, 2001T89C51RD2API call ParameterREAD copy of the deviceID#1Input Parameters:R0 = osc freq (integer Not required, left for Phil

Rev. F - 15 February, 2001 64T89C51RD2Note: These functions can only be called by user’s code. The standard boot loader cannot decrease the security l

65 Rev. F - 15 February, 2001T89C51RD2Mode Name Mode Rst PsenAle__|_|EA P2.6 P2.7 P3.6 P3.7 P0[7..0]PELCKProgram or Erase Lock.Disable the Erasure or

Rev. F - 15 February, 2001 66T89C51RD2Note 1: P3.2 is pulled low during programming to indicate RDY/BUSY.(P3.2 = 1 Ready; P3.2 = 0 Busy).Note 2: In Pa

67 Rev. F - 15 February, 2001T89C51RD2Figure 22. Set-Up Modes Configuration8.9.4. Programming AlgorithmTo program the T89C51RD2 the following sequence

Rev. F - 15 February, 2001 68T89C51RD2• Step 8: Input the valid address on the address lines.• Step 9: Pulse ALE/PROG once until P3.2 is high or the s

69 Rev. F - 15 February, 2001T89C51RD2All other addresses are reservedCopy of device ID #2 0060h FChCopy of device ID #1 0031h D7hCopy of Manufacturer

Rev. F - 15 February, 2001 7T89C51RD2MnemonicPin NumberTypeName and FunctionDIL LCC VQFP 1.4VSS20 22 16 I Ground: 0V referenceVss1 1 39 I Optional Gro

Rev. F - 15 February, 2001 70T89C51RD29. Electrical Characteristics9.1. Absolute Maximum Ratings(1)Ambiant Temperature Under Bias:C = commercial 0°Cto

71 Rev. F - 15 February, 2001T89C51RD29.2. DC Parameters for Standard Voltage (1)TA =0°Cto+70°C; VSS=0V;VCC=5V± 10%;F=0to40MHz.TA = -40°Cto+85°C; VSS=

Rev. F - 15 February, 2001 72T89C51RD29.3. DC Parameters for Standard Voltage (2)TA =0°Cto+70°C; VSS=0V;VCC=3Vto5.5V;F=0to33MHz.TA = -40°Cto+85°C; VSS

73 Rev. F - 15 February, 2001T89C51RD29.4. DC Parameters for Low VoltageTA =0°Cto+70°C; VSS=0V;VCC=2.7Vto3.6V;F=0to25MHz.TA = -40°Cto+85°C; VSS=0V;VCC

Rev. F - 15 February, 2001 74T89C51RD2Figure 24. ICCTest Condition, Active ModeFigure 25. ICCTest Condition, Idle ModeFigure 26. ICCTest Condition, Po

75 Rev. F - 15 February, 2001T89C51RD2Figure 27. Clock Signal Waveform for ICCTests in Active and Idle Modes9.5. AC Parameters9.5.1. Explanation of th

Rev. F - 15 February, 2001 76T89C51RD29.5.2. External Program Memory CharacteristicsTable 38. Symbol DescriptionSymbol ParameterT Oscillator clock per

77 Rev. F - 15 February, 2001T89C51RD29.5.3. External Program Memory Read CycleTable 40. AC Parameters for a Variable ClockSymbol Type StandardClockX2

Rev. F - 15 February, 2001 78T89C51RD29.5.4. External Data Memory CharacteristicsTable 41. Symbol DescriptionSymbol ParameterTRLRHRD Pulse WidthTWLWHW

79 Rev. F - 15 February, 2001T89C51RD2Table 42. AC Parameters for a Fix ClockSymbol -M -L UnitsMin Max Min MaxTRLRH130 130 nsTWLWH130 130 nsTRLDV100 1

8 Rev. F - 15 February, 2001T89C51RD2MnemonicPin NumberTypeName and FunctionDIL LCC VQFP 1.417 19 13 O RD (P3.7): External data memory read strobeRese

Rev. F - 15 February, 2001 80T89C51RD29.5.5. External Data Memory Write CycleTable 43. AC Parameters for a Variable ClockSymbol Type StandardClockX2 C

81 Rev. F - 15 February, 2001T89C51RD29.5.6. External Data Memory Read Cycle9.5.7. Serial Port Timing - Shift Register ModeTable 44. Symbol Descriptio

Rev. F - 15 February, 2001 82T89C51RD29.5.8. Shift Register Timing WaveformsTable 46. AC Parameters for a Variable ClockSymbol Type StandardClockX2 Cl

83 Rev. F - 15 February, 2001T89C51RD29.5.9. FLASH EEPROM Programming and Verification CharacteristicsTA =21°Cto27°C; VSS= 0V; VCC=5V± 10%.9.5.10. FLA

Rev. F - 15 February, 2001 84T89C51RD29.5.11. External Clock Drive Characteristics (XTAL1)Table 48. AC Parameters9.5.12. External Clock Drive Waveform

85 Rev. F - 15 February, 2001T89C51RD29.5.15. Clock WaveformsValid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.This diagram indi

Rev. F - 15 February, 2001 86T89C51RD210. Ordering InformationPackages:3C: PDIL40SL: PLCC44RL: VQFP44 (1.4mm)SM: PLCC68RD: VQFP64, square-package (1.

Rev. F - 15 February, 2001 9T89C51RD25.1. Pin Description for 64/68 pin PackagesPort 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull