MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
28 ______________________________________________________________________________________
A third pole occurs due to the input capacitance of the
NMOS transistor’s gate, C
q
(C
iss
from the MOSFET
data sheet), and the compensation resistor (R
A
). If an
NPN bipolar transistor is used instead, this third pole
can be calculated from the base capacitance (C
q
=
C
IBO
from the NPN data sheet). To ensure stability, a
zero is added to the loop from the resistor (R
A
) and
capacitor (C
A
).
For good stability and transient response, first pick
C
OUT2
at approximately 6.8µF/A of load current. For the
Typical Applications Circuit, C
OUT2
is a 10µF ceramic
capacitor. Ensure that the zero formed from the ESR of
C
OUT2
is greater than the maximum bandwidth BW
MAX
(calculated below). The maximum bandwidth should
also be less than the pole created by Q3’s gate capaci-
tance (Cq) and the compensation resistor (R
A
).
The following equations set the compensation zero a
decade and a half below the maximum load pole and
ensure the above constraint is met. Choose the larger
of the two values for C
A
.
MOSFET Transistor Selection
MAX8513/MAX8514s’ OUT2 uses N-channel MOSFETs
as the series pass transistor to improve efficiency for
high output current by not requiring a large amount of
drive current. The selected MOSFET must have the gate
threshold voltage meet the following criteria:
where V
DRV2
is equal to 7.75V or V
SUP2
- 1.5V
(whichever is less), and V
GSMAX
is the maximum gate
voltage required to yield the on-resistance specified by
the manufacturer’s data sheet. Logic-gate MOSFETs
are recommended.
NPN-Transistor Selection
The MAX8513/MAX8514s’ OUT2 can use a less expen-
sive NPN transistor as the series pass transistor. In
selecting the appropriate NPN transistor, make sure the
beta is large enough so the regulator can provide
enough base current. The minimum beta of the transis-
tor is:
In addition, to avoid premature dropout, V
CE_SAT
≤
V
IN_MIN -
V
OUT2
.
OUT3_ Transistor Selection
The pass transistors must meet specifications for cur-
rent gain (β), input capacitance, collector-emitter satu-
ration voltage, and power dissipation. The transistor’s
current gain limits the guaranteed maximum output cur-
rent to:
where I
DRV3P_MIN
is the minimum base-drive current
and R12 is the pullup resistor connected between the
transistor’s base and emitter (see the Typical
Applications Circuits). In addition, to avoid premature
dropout V
CE_SAT
≤ V
IN_MIN -
V
OUT3
. Furthermore, the
transistor’s current gain increases the linear regulator’s
DC loop gain (see the Stability Requirements section),
so excessive gain destabilizes the output. Therefore,
transistors with current gain over 100 at the maximum
output current, such as Darlington transistors, are not
recommended. The transistor’s input capacitance and
input resistance also create a second pole, which could
be low enough to destabilize the LDO when the output
is heavily loaded.
The transistor’s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator supports. Alternately,
.
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