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T89C51CC01

Rev. D – 17-Dec-01

14.1 WatchDog

Programming

The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the

WDT duration.

Table 32. Machine Cycle Count

To compute WD Time-Out, the following formula is applied:

Note: Svalue represents the decimal value of (S2 S1 S0)

Find Hereafter computed Time-Out value for Fosc

XTAL

= 12MHz in X1 mode

Table 33. Time-Out Computation

14.2 WatchDog Timer

during Power down

mode and Idle

In Power Down mode the oscillator stops, which means the WDT also stops. While in

Power Down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power Down mode: by a hardware reset or via a level activated external interrupt

which is enabled prior to entering Power Down mode. When Power Down is exited with

hardware reset, the watchdog is disabled. Exiting Power Down with an interrupt is signif-

icantly different. The interrupt shall be held low long enough for the oscillator to stabilize.

When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from

resetting the device while the interrupt pin is held low, the WDT is not started until the

S2 S1 S0 Machine Cycle Count

000 2

-1

001 2

-1

010 2

-1

011 2

-1

100 2

-1

101 2

-1

110 2

-1

111 2

-1

S2 S1 S0 Fosc=12MHz Fosc=16MHz Fosc=20MHz

0 0 0 16.38 ms 12.28 ms 9.82 ms

0 0 1 32.77 ms 24.57 ms 19.66 ms

0 1 0 65.54 ms 49.14 ms 39.32 ms

0 1 1 131.07 ms 98.28 ms 78.64 ms

1 0 0 262.14ms 196.56ms 157.28ms

1 0 1 524.29ms 393.12ms 314.56ms

1 1 0 1.05 s 786.24 ms 629.12 ms

1 1 1 2.10 s 1.57 s 1.25 ms

FTime Out

12 2

Svalue

×()1–()×

-------------------------------------------------------------------

=–

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 148 149

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