Rainbow-electronics ATF1504ASVL Bedienungsanleitung

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1
Features
High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
3.0 to 3.6V Operating Range
64 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
44, 68, 84, 100 Pins
15nsMaximumPin-to-pinDelay
Registered Operation up to 77 MHz
Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
D/T/Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open-collector Option
Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
Automatic 5 µA Standby for “L Version
Pin-controlled 100 µA Standby Mode (Typical)
Programmable Pin-keeper Circuits on Inputs and I/Os
Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
Edge-controlled Power-down “L
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs and I/O
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
Rev. 1409H–PLD–09/02
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Inhaltsverzeichnis

Seite 1 - Enhanced Features

1Features• High-density, High-performance, Electrically-erasable ComplexProgrammable Logic Device– 3.0 to 3.6V Operating Range– 64 Macrocells– 5 Produ

Seite 2

10ATF1504ASV(L)1409H–PLD–09/02Programming ATF1504ASV(L)devicesare in-system programmable (ISP)devices utilizing the4-pinJTAG protocol. This capability

Seite 3

11ATF1504ASV(L)1409H–PLD–09/02Notes: 1. Not more than one output at a time should be shorted.Duration of short circuit test should not exceed30 sec.2.

Seite 4

12ATF1504ASV(L)1409H–PLD–09/02Timing ModelAbsolute Maximum Ratings*Temperature UnderBias... -40°Cto+85°C*NOTICE: Stress

Seite 5

13ATF1504ASV(L)1409H–PLD–09/02AC CharacteristicsSymbol Parameter-15 -20UnitsMin Max Min MaxtPD1Input or Feedback to Non-Registered Output 3 15 20 nstP

Seite 6

14ATF1504ASV(L)1409H–PLD–09/02Notes: 1. See ordering information for valid part numbers.2. The tRPAparametermustbe addedtothe tLAD,tLAC,tTIC,tACL,andt

Seite 7

15ATF1504ASV(L)1409H–PLD–09/02Power-down Mode The ATF1504ASV(L)includes an optional pin-controlledpower-down feature. Whenthismode is enabled, thePDpi

Seite 8

16ATF1504ASV(L)1409H–PLD–09/02JTAG-BST/ISPOverviewThe JTAG boundary-scan testing is controlledbythe Test Access Port (TAP)controllerin the ATF1504ASV(

Seite 9

17ATF1504ASV(L)1409H–PLD–09/02BSC Configuration for Macrocell01DQ0101DQDQCaptureDRCaptureDRUpdateDR0101DQDQTDITDIOUTJOEJShiftShiftClockClockModeTDOTDO

Seite 10 - ATF1504ASV(L)

18ATF1504ASV(L)1409H–PLD–09/02OE (1, 2) Global OE pinsGCLR Global Clear pinGCLK(1, 2, 3) Global Clock pinsPD (1, 2) Power-down pinsTDI, TMS, TCK, TDOJ

Seite 11

19ATF1504ASV(L)1409H–PLD–09/02ATF1504ASV I/O PinoutsMC PLC44-leadPLCC44-leadTQFP68-leadPLCC84-leadPLCC100-leadPQFP100-leadTQFP MC PLC44-leadPLCC44-lea

Seite 12

2ATF1504ASV(L)1409H–PLD–09/0244-lead TQFPTop View12345678910113332313029282726252423I/O/TDII/OI/OGNDPD1/I/OI/OTMS/I/OI/OVCCI/OI/OI/OI/O/TDOI/OI/OVCCI/

Seite 13

20ATF1504ASV(L)1409H–PLD–09/02SUPPLY CURRENT VS. SUPPLY VOLTAGE(TA= 25°C, F = 0)02550751002.502.75 3.00 3.253.50 3.75 4.00SUPPLYVOLTAGE (V)ICC(mA)STAN

Seite 14

21ATF1504ASV(L)1409H–PLD–09/02OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE(VCC=3.3V,TA= 25°C)02040608010000.5 11.5 22.533.5 4OUTPUT VOLTAGE (V)IOL(mA)INPUT

Seite 15

22ATF1504ASV(L)1409H–PLD–09/02Using “C” Product for IndustrialThere is very little risk in using “C” devices for industrial applications because the V

Seite 16

23ATF1504ASV(L)1409H–PLD–09/02Packaging Information44A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 44A, 44-lead, 10 x 10 m

Seite 17

24ATF1504ASV(L)1409H–PLD–09/0244J–PLCCNotes: 1. This package conforms to JEDEC reference MS-018, Variation AC.2. Dimensions D1 and E1 do not include m

Seite 18

25ATF1504ASV(L)1409H–PLD–09/0268J–PLCC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV.68J, 68-lead, Plastic J-leaded Chip Carrier (PLCC)B68

Seite 19

26ATF1504ASV(L)1409H–PLD–09/0284J–PLCC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV.84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)B84

Seite 20

27ATF1504ASV(L)1409H–PLD–09/02100Q1 – PQFPPIN1ID16.95 (0.667)17.45 (0.687)19.90 (0.783)20.10 (0.791)22.95 (0.904)23.45 (0.923)0.65 (0.0256) BSC0.22 (0

Seite 21

28ATF1504ASV(L)1409H–PLD–09/02100A – TQFP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 100A, 100-lead, 14 x 14 mm Body Size, 1.0 m

Seite 22

Printedonrecycledpaper.1409H–PLD–09/02 xM© Atmel Corporation 2002.Atmel Corporation makesnowarrantyforthe use of its products, other than thoseexpress

Seite 23

3ATF1504ASV(L)1409H–PLD–09/02100-lead PQFPTop View1234567891011121314151617181920212223242526272829308079787776757473727170696867666564636261605958575

Seite 24

4ATF1504ASV(L)1409H–PLD–09/02Description The ATF1504ASV(L) is a high-performance, high-density complex programmable logicdevice (CPLD) that utilizesAt

Seite 25

5ATF1504ASV(L)1409H–PLD–09/02Block DiagramUnused product terms are automatically disabledbythe compilertodecrease powerconsumption. Asecurity fuse,whe

Seite 26

6ATF1504ASV(L)1409H–PLD–09/02OR/XOR/CASCADE Logic The ATF1504ASV(L)’s logic structure is designedtoefficiently support all types of logic.Within a sin

Seite 27

7ATF1504ASV(L)1409H–PLD–09/02Figure 1. ATF1504ASV(L)MacrocellProgrammable Pin-keeper Option for Inputs and I/OsThe ATF1504ASV(L)offers the option of p

Seite 28

8ATF1504ASV(L)1409H–PLD–09/02Input DiagramI/O DiagramSpeed/PowerManagementThe ATF1504ASV(L) has several built-in speed and power management features.

Seite 29 - 1409H–PLD–09/02 xM

9ATF1504ASV(L)1409H–PLD–09/02All power-down AC characteristic parameters are computedfromexternal input or I/Opins, with reduced-powerbitturnedon. For

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