
BR24L01A-W / BR24L01AF-W / BR24L01AFJ-W /
Memory ICs
BR24L01AFV-W / BR24L01AFVM-W
12/25
z
Sequential read
S
T
A
R
T
SLAVE
ADDRESS
R
/
W
A
C
K
A
C
K
A
C
K
A
C
K
R
E
A
D
DATA(n)
DATA(n+x)
SDA
LINE
1100A2
A1 A0
D7 D7D0 D0
S
T
O
P
Fig.12 SEQUENTIAL READ CYCLE TIMING
(Current Read)
•
If an Acknowledge is detected, and no STOP condition is generated by the master (
µ
-COM), the device will continue to
transmit the data.
[
It can transmit all data (1kbit 128word)
]
•
If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition
before returning to the standby mode.
•
The Sequential Read operation can be performed with both Current Read and Random Read.
Note) If an Acknowledge is detected with “Low” level, not “High” level, command will become Sequential Read.
So the device transmits the next data, Read is not terminated. In the case of terminating Read, input
Acknowledge with “High” always, then input stop condition.
Kommentare zu diesen Handbüchern