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BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W
Memory ICs
1/25
4k
×
8 bit electrically erasable PROM
BR24L32-W / BR24L32F-W / BR24L32FJ-W
BR24L32FV-W
The BR24L32-W series is 2-wire (I
2
C BUS type) serial EEPROMs which are electrically programmable.
I
2
C BUS is a registered trademark of Philips.
z
Applications
General purpose
z
Features
1) 4k registers
×
8 bits serial architecture.
2) Single power supply (1.8V to 5.5V).
3) Two wire serial interface.
4) Automatic erase.
5) 32byte Page Write Mode.
6) Low power consumption.
Write
(5V) : 1.5mA (Typ.)
Read (5V) : 0.2mA (Typ.)
Standby (5V) : 0.1
µ
A (Typ.)
7) DATA security
Write protect feature (WP pin).
Inhibit to WRITE at low V
CC
.
8) Small package - - - DIP8 / SOP8 / SSOP-B8 pin
9) High reliability EEPROM with Double-Cell structure.
10) High reliability fine pattern CMOS technology.
11) Endurance : 1,000,000 erase / write cycles
12) Data retention : 40 years
13) Filtered inputs in SCL,SDA for noise suppression.
14) Initial data FFh in all address.
z
Absolute maximum ratings
(Ta=25
°
C)
Parameter Symbol Limits Unit
Supply voltage 0.3 to +6.5 V
Power dissipation mW
Storage temperature
65 to +125
°C
Operating temperature
°C
Terminal voltage
V
40 to +85
V
CC
0.3 to V
CC
+0.3
Pd
Tstg
Topr
1
450(SOP8)
800(DIP8)
2
3
300(SSOP-B8)
1 Degradation is done at 8.0mW/°C for operation above 25°C.
2,3 Degradation is done at 4.5mW/°C for operation above 25°C.
4 Degradation is done at 3.0mW/°C for operation above 25°C.
450(SOP-J8)
4
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Inhaltsverzeichnis

Seite 1 - BR24L32FV-W

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs1/254k×8 bit electrically erasable PROMBR24L32-W / BR24L32F-W / BR24L32FJ-WBR24L32

Seite 2

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs10/25zByte writeSDALINEWPSTARTSLAVEADDRESS10 01R/WWRITEACKACKD7DATAD0STOPFig.8 BY

Seite 3 - Dimension

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs11/25zCurrent readSDALINESTARTSLAVEADDRESS11R/WACKACKDATASTOP00A2 A1 A0D7 D0READFi

Seite 4

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs12/25zSequential readSTARTSLAVEADDRESSR/WACKACKACKACKREADDATA(n)DATA(n+x)SDALINE11

Seite 5

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs13/25zApplication1) WP effective timing WP is fixed to “H” or “L” usually. But

Seite 6

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs14/252) Software reset Please execute software reset in case that the device is

Seite 7

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs15/253) Acknowledge polling Since the device ignore all input commands during t

Seite 8 - A2 A1 A01010 R / W

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs16/254) Command cancellation by start and stop condition During a command input

Seite 9

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs17/255) Notes for power supply VCC rises through the low voltage region in which

Seite 10

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs18/256) I / O circuit • Pull up resister of SDA pin The pull up resister is n

Seite 11 - Memory ICs

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs19/25 • The minimum value RPU The minimum value of RPU is determined by followin

Seite 12

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs2/25zRecommended operating conditions (Ta=25°C)Parameter Symbol Limits UnitSupply

Seite 13

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs20/258) Notes for noise on VCC • About bypass capacitor Noise and surges on p

Seite 14

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs21/25 • The maximum value of RS The maximum value of RS is determined by followi

Seite 15

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs22/2510) The special character DATA The following characteristic data are typ

Seite 16

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs23/2520.60.50.40.30.20.1001 34 65CURRENT CONSUMPTION AT READING : ICC2 (mA)Fig.2

Seite 17

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs24/2523001002000−100−20001 34 65INPUT DATA SET UP TIME : tSU:DAT (ns)Fig.35 I

Seite 18

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs25/2520.60.30.40.50.20.1001 34 65NOISE REDUCTION EFFECTIVE TIME : tI (SCL H) (µ

Seite 19

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs3/25zDimensionFig.1(a) PHYSICAL DIMENSION (Units : mm) DIP8 (BR24L32-W) 0.5±0.13

Seite 20

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs4/25zBlock diagram1A0A1 2A2 3GND 4VCC8WP76 SCLSDA532kbit EEPROM arrayControl logic

Seite 21

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs5/25zAC operating characteristics (Unless otherwise specified Ta=−40 to 85°C, VCC=

Seite 22

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs6/25zSynchronous data timingtBUFtPDtHIGH tHD : STA tLOWtFtRSCLSTART BIT STOP BITSC

Seite 23

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs7/25zWP timingSCLSDAWPtHD : WPtWRSTOP BITACKACKD1DATA (n)DATA (1)tSU : WPD0Fig.6(a

Seite 24

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs8/25zDevice operation1) Start condition (Recognition of start bit) • All commands

Seite 25

BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-WMemory ICs9/256) Acknowledge • Acknowledge is a software convention used to indicate success

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