
BR24L32-W / BR24L32F-W / BR24L32FJ-W / BR24L32FV-W
Memory ICs
4/25
z
Block diagram
1
A0
A1 2
A2 3
GND 4
V
CC
8
WP7
6 SCL
SDA5
32kbit EEPROM array
Control logic
High voltage generator Vcc level detect
12bit
8bit
ACK
STOPSTART
Address
decoder
Slave word
address register
12bits
Data
register
Fig.2 BLOCK DIAGRAM
z
Pin configuration
BR24L32-W
BR24L32F-W
BR24L32FJ-W
BR24L32FV-W
V
CC
A0
WP
A1
SCL
A2
SDA
GND
1234
5678
Fig.3 PIN LAYOUT
z
Pin name
Write protect input
Power supply
Function
Ground (0V)
Slave address set
Serial clock input
SDA
V
CC
A0, A1, A2
Pin name
GND
WP
SCL
I / O
−
−
IN
IN
IN
IN / OUT
Slave and word address,
serial data input, serial data output
∗ An open drain output requires a pull-up resistor.
∗
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