Rainbow-electronics W9864G6GB Bedienungsanleitung

W9864G6GB 1M × 4 BANKS × 16 BITS SDRAM Publication Release Date: August 14, 2006 - 1 - Revision A01 Table of Contents- 1. GENERAL DESCRIPTION...

W9864G6GB - 10 - 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is ente

W9864G6GB Publication Release Date: August 14, 2006 - 11 - Revision A01 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low.

W9864G6GB - 12 - 8. TABLE OF OPERATING MODES Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1

W9864G6GB Publication Release Date: August 14, 2006 - 13 - Revision A01 8.1 Simplified State Diagram ModeRegisterSetIDLECBRRefreshSelfRefreshROW

W9864G6GB - 14 - 9. ABSOLUTE MAXIMUM RATING PARAMETER SYM. RATING UNIT NOTES Input, Column Output Voltage(-7) VIN, VOUT 2.7V~3.6V V 1 Power Suppl

W9864G6GB Publication Release Date: August 14, 2006 - 15 - Revision A01 12. DC CHARACTERISTICS (VCC=2.7V~3.6V, TA = 0 to 70°C ) PARAMETER SYM. -

W9864G6GB - 16 - 13. AC CHARACTERISTICS (VCC = 2.7V~3.6V, VSS = 0V,TA = 0 to 70°C ) (Notes: 5, 6.) -7 PARAMETER SYM. MIN. MAX. UNIT NOTERef/Active to

W9864G6GB Publication Release Date: August 14, 2006 - 17 - Revision A01 Notes: 1. Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent

W9864G6GB - 18 - (2) A.C Latency Characteristics CKE to clock disable (CKE Latency) 1 tCK DQM to output to HI-Z (Read DQM Latency) 2 DQM to out

W9864G6GB Publication Release Date: August 14, 2006 - 19 - Revision A01 14. TIMING WAVEFORMS 14.1 Command Input Timing tCKCLKA0-A10BS0, 1VIHVILtC

W9864G6GB - 2 - 11. CAPACITANCE...

W9864G6GB - 20 - 14.2 Read Timing Read CAS LatencytACtLZtACtOHtHZtOHBurst LengthRead CommandCLKCSRASCASWEA0-A10BS0, 1DQValidData-OutValidData-Out

W9864G6GB Publication Release Date: August 14, 2006 - 21 - Revision A01 14.3 Control Timing of Input Data *DQM2,3="L"CLK(Word Mask)tCMH

W9864G6GB - 22 - 14.4 Control Timing of Output Data DQ0 -DQ7ValidData-OutValidData-OutValidData-OuttOHtACtOHtACtOHtHZtLZtACtOHtACOPENCLK(Output Enab

W9864G6GB Publication Release Date: August 14, 2006 - 23 - Revision A01 14.5 Mode Register Set Cycle A0A1A2A3A4A5A6Burst LengthAddressing ModeCAS

W9864G6GB - 24 - 15. OPERATING TIMING EXAMPLE 15.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 01 2 3 4 56 7 8 9 10 11 12 13 14 15 16

W9864G6GB Publication Release Date: August 14, 2006 - 25 - Revision A01 15.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecha

W9864G6GB - 26 - 15.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 01 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 1819 20 21 22 23tRCtRAStRP

W9864G6GB Publication Release Date: August 14, 2006 - 27 - Revision A01 15.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecha

W9864G6GB - 28 - 15.5 Interleaved Bank Write (Burst Length = 8) 01 2 3 4 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23tRCtRAStRPtRAStRCDtRCDtRC

W9864G6GB Publication Release Date: August 14, 2006 - 29 - Revision A01 15.6 Interleaved Bank Write (Burst Length = 8, Autoprecharge) 0 1 2 3 4 5

W9864G6GB Publication Release Date: August 14, 2006 - 3 - Revision A01 1. GENERAL DESCRIPTION W9864G6GB is a high-speed synchronous dynamic random

W9864G6GB - 30 - 15.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23tCCDtCCDtCCDtR

W9864G6GB Publication Release Date: August 14, 2006 - 31 - Revision A01 15.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) 01 2 3 4 56

W9864G6GB - 32 - 15.9 Autoprecharge Read (Burst Length = 4, CAS Latency = 3) 01 2 3456 7 89 1011 12 1314 1516 17 1819202122 23(CLK = 100 MHz)CLKDQCK

W9864G6GB Publication Release Date: August 14, 2006 - 33 - Revision A01 15.10 Autoprecharge Write (Burst Length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12

W9864G6GB - 34 - 15.11 Autorefresh Cycle 01 2 3456 7 89 1011 12 1314 1516 17 1819202122 23(CLK = 100 MHz)All BanksPrechageAutoRefreshAuto Refresh (Ar

W9864G6GB Publication Release Date: August 14, 2006 - 35 - Revision A01 15.12 Self-refresh Cycle 01 2 3456 7 89 1011 12 1314 1516 17 1819202122 23

W9864G6GB - 36 - 15.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) 01 2 3456 7 89 1011 12 1314 1516 17 1819202122 23CLK(CLK = 100

W9864G6GB Publication Release Date: August 14, 2006 - 37 - Revision A01 15.14 Power-down Mode 01 2 3456 7 89 1011 12 1314 1516 17 1819202122 23(CL

W9864G6GB - 38 - 15.15 Auto-precharge Timing (Write Cycle) Act01 32(1) CAS Latency = 2(a) burst length = 1DQ45 76891110WriteD0ActAPCommand(b) burst

W9864G6GB Publication Release Date: August 14, 2006 - 39 - Revision A01 15.16 Auto-precharge Timing (Read Cycle) Read AP0 1110987654321Q0Q0Read A

W9864G6GB - 4 - 4. PIN CONFIGURATION Top View 762 1 C B A P N G D E M H L F K R J VSS VSS DQ14 DQ13 DQ12 DQ10 DQ8 NC NC NC CKE A11 A8 A6 DQ9 DQ15 A4

W9864G6GB - 40 - 15.17 Timing Chart of Read to Write Cycle Note: The Output data must be masked by DQM to avoid I/O conflict.Read Write1110987654321

W9864G6GB Publication Release Date: August 14, 2006 - 41 - Revision A01 15.18 Timing Chart of Write to Read Cycle 01110987654321In the case of Bu

W9864G6GB - 42 - 15.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) Read BST0 1110987654321DQQ0 Q1 Q2 Q3BST( a ) CAS latency =2Command ( b

W9864G6GB Publication Release Date: August 14, 2006 - 43 - Revision A01 15.20 CKE/DQM Input Timing (Write Cycle) 7654321CKE MASK( 1 )D1 D6D5D3D2C

W9864G6GB - 44 - 15.21 CKE/DQM Input Timing (Read Cycle) 7654321( 1 )Q1Q6Q4Q3Q2CLK cycle No.ExternalInternalCKEDQMDQOpen Open7654321Q1Q6Q3Q2CLK cycl

W9864G6GB Publication Release Date: August 14, 2006 - 45 - Revision A01 15.22 Self Refresh/Power Down Mode Exit Timing Asynchronous Control In

W9864G6GB - 46 - 16. PACKAGE DIMENSIONS VFBGA60Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø=0.4mm)

W9864G6GB Publication Release Date: August 14, 2006 - 47 - Revision A01 17. VERSION HISTORY VERSION DATE PAGE DESCRIPTION A01 8/14/2006 ALL CREA

W9864G6GB Publication Release Date: August 14, 2006 - 5 - Revision A01 5. PIN DESCRIPTION BALL LOCATION PIN NAME FUNCTION DESCRIPTION M1,M2,N1,

W9864G6GB - 6 - 6. BLOCK DIAGRAM DQ0DQ15UDQMLDQMCLKCKEA10CLOCKBUFFERCOMMANDDECODERADDRESSBUFFERREFRESHCOUNTERCOLUMNCOUNTERCONTROLSIGNALGENERATORMODER

W9864G6GB Publication Release Date: August 14, 2006 - 7 - Revision A01 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default powe

W9864G6GB - 8 - 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE h

W9864G6GB Publication Release Date: August 14, 2006 - 9 - Revision A01 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the