
DS1857
Dual Temperature-Controlled Resistors with
External Temperature Input and Monitors
____________________________________________________________________ 13
MEMORY
LOCATION
(hex)
EEPROM/
SRAM
SETTING
FUNCTION
1C to 5F EEPROM — 00 Reserved —
60 to 61 SRAM R —
Measured TMP
(MSB to LSB)
Digitized measured value for temperature.
See Table 1.
62 to 63 SRAM R —
Measured V
CC
(MSB to LSB)
Digitized measured value for V
CC
.
See Table 1.
64 to 65 SRAM R —
Measured MON1
(MSB to LSB)
Digitized measured value for MON1.
See Table 1.
66 to 67 SRAM R —
Measured MON2
(MSB to LSB)
Digitized measured value for MON2.
See Table 1.
68 to 6D SRAM R — Reserved —
6E SRAM — — Logic states —
Bit 7 — R X HIZSTA
Resistor status bit. A high indicates that both
resistors are in high-impedance mode. A low
indicates that both resistors are operating
R/W
Resistor control bit. Setting this bit high
causes both resistors to go into a high-
impedance state.
5——X X —
4——X X —
3——X X —
2——X X —
1——X X —
0—RX RDYB
This status bit goes high when V
CC
has fallen
below the POA level.
6F SRAM — — Conversion updates —
Bit 7 —
R/W
This bit goes high after a temperature and
address update has occurred for the
corresponding measurement in bytes 60h to
61h. This bit can be written to a 0 by the user
and monitored to verify that a conversion has
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