
DS2422
10 of 48
Figure 5. 64-Bit Lasered ROM
MSB LSB
8-Bit
CRC Code
48-Bit Serial Number
8-Bit Family
Code (41h)
MSB LSB MSB LSB MSB LSB
Figure 6. 1-Wire CRC Generator
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
Polynomial = X
8
+ X
5
+ X
4
+ 1
1
st
STAGE
2
nd
STAGE
3
rd
STAGE
4
th
STAGE
6
th
STAGE
5
th
STAGE
7
th
STAGE
8
th
STAGE
INPUT DATA
Figure 7. DS2422 Memory Map
32-Byte Intermediate Storage Scratchpad
DDRESS
0000H to
001FH
32-Byte General-Purpose SRAM (R/W)
Page 0
0020H to
01FFH
General-Purpose SRAM (R/W)
Pages 1
to 15
0200H to
021FH
32-Byte Register Page 1
Page 16
0220H to
023FH
32-Byte Register Page 2
Page 17
0240H to
025FH
Calibration Memory Page 1 (R/W)
Page 18
0260H to
027FH
Calibration Memory Page 2 (R/W)
Page 19
0280H to
03FFH
(Reserved For Future Extensions) Pages 20 to 31
0400H to
041FH
Trim Register Page (R/W)
Page 32
0420H to
0FFFH
(Reserved For Future Extensions) Pages 33 to 127
1000H to
2FFFH
Datalog Memory (Read-Only)
Pages 128
to 383
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