General DescriptionThe MAX3420E contains the digital logic and analogcircuitry necessary to implement a full-speed USBperipheral compliant to USB spec
MAX3420EUSB Peripheral Controllerwith SPI Interface10 ______________________________________________________________________________________Note 1: Pa
MAX3420EUSB Peripheral Controllerwith SPI Interface______________________________________________________________________________________ 11Test Circu
MAX3420EUSB Peripheral Controllerwith SPI Interface12 ______________________________________________________________________________________Typical Op
(NOVBUSIRQ)) and disconnect the internal 1.5kΩpullup resistor. If the device using the MAX3420E isbus powered (through a +3.3V regulator connected toV
MAX3420E(R17) register to make INT active high, and clear thePOSINT bit to make INT active low.GPIN3–GPIN0, GPOUT3–GPOUT0 and GPXThe MAX3420E has four
In full-duplex mode (FDUPSPI=1), the MOSI and MISOpins are separate, and the MISO pin drives only when SSis low. In this mode, the first eight SCLK ed
MAX3420ESPI Half- and Full-Duplex OperationThe MAX3420E can be programmed to operate in half-duplex (a bidirectional data pin) or full-duplex (onedata
(5) To write SPI data, the SPI master keeps its outputdriver on and clocks subsequent bytes into theMOSI pin. To read SPI data, after the eighth clock
MAX3420Epre-shutdown tasks before it requests the MAX3420E toenter the power-down state by setting PWRDOWN = 1.Wakeup and USB ResumeThe MAX3420E may w
MAX3420E in a Bus-Powered ApplicationFigure 16 depicts the MAX3420E in a peripheral devicethat is powered by VBUS. This configuration is advanta-geous
The MAX3420E connects to any microprocessor using3 or 4 interface pins (Figure 1). On a simple micro-processor without SPI hardware, these can be bit-
MAX3420Ewhether the USB device is plugged in or not, it needssome way to detect a plug-in event. A comparatorinside the MAX3420E checks for a valid VB
capacitors connected to ground as close to the pins aspossible. D+, D-, and VBCOMP provide protection tothe following limits:• ±15kV using the Human B
MAX3420EUSB Peripheral Controllerwith SPI Interface22 ______________________________________________________________________________________Package In
MAX3420EUSB Peripheral Controllerwith SPI InterfaceMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied
MAX3420EUSB Peripheral Controllerwith SPI Interface_______________________________________________________________________________________ 3Functional
MAX3420EUSB Peripheral Controllerwith SPI Interface4 _______________________________________________________________________________________Pin Descri
Register DescriptionThe SPI master controls the MAX3420E by reading andwriting 21 registers (Table 1). For a complete descrip-tion of register content
MAX3420Emode, these status bits are accessed in the normalway, as register bits.The first five registers (R0–R4) access endpoint FIFOs.To access a FIF
MAX3420EUSB Peripheral Controllerwith SPI Interface_______________________________________________________________________________________ 7TQFNMAX342
MAX3420EUSB Peripheral Controllerwith SPI Interface8 _______________________________________________________________________________________ABSOLUTE M
MAX3420EUSB Peripheral Controllerwith SPI Interface_______________________________________________________________________________________ 9ELECTRICAL
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