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General Description
The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A
built-in full-speed transceiver features ±15kV ESD pro-
tection and programmable USB connect and discon-
nect. An internal SIE (serial-interface engine) handles
low-level USB protocol details such as error checking
and bus retries. The MAX3420E operates using a regis-
ter set accessed by an SPI interface that operates up to
26MHz. Any SPI master (microprocessor, ASIC, DSP,
etc.) can add USB functionality using the simple 3- or
4-wire SPI interface.
Internal level translators allow the SPI interface to run at
a system voltage between 1.71V and 3.6V. USB timed
operations are done inside the MAX3420E with inter-
rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3420E includes four general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
The MAX3420E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
TQFP package (7mm x 7mm) and a space-saving 24-
pin TQFN package (4mm x 4mm).
Applications
Features
Microprocessor-Independent USB Solution
Complies with USB Specification Revision 2.0
(Full-Speed Operation)
Integrated Full-Speed USB Transceiver
Firmware/Hardware Control of an Internal D+
Pullup Resistor
Programmable 3- or 4-Wire 26MHz SPI Interface
Level Translators and V
L
Input Allow Independent
System Interface Voltage
Internal Comparator Detects V
BUS
for
Self-Powered Applications
ESD Protection on D+, D-, and VBCOMP
Interrupt Output Pin (Level or Programmable
Edge) Allows Polled or Interrupt-Driven SPI
Interface
Intelligent USB Serial Interface Engine (SIE)
Automatically Handles USB Flow Control and
Double Buffering
Handles Low-Level USB Signaling Details
Contains Timers for USB Time-Sensitive
Operations So SPI Master Does Not Need to
Time Events
Built-In Endpoint FIFOs:
EP0: CONTROL (64 Bytes)
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, Bulk or Interrupt (64 Bytes)
Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrently with USB Transfers
Over the Same Endpoint
SETUP Data Has Its Own 8-Byte FIFO, Simplifying
Firmware
Four General-Purpose Inputs and Four General-
Purpose Outputs
Space-Saving TQFP and TQFN Packages
MAX3420E
USB Peripheral Controller
with SPI Interface
________________________________________________________________ Maxim Integrated Products 1
19-3781; Rev 0; 8/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Cell Phones
PC Peripherals
Microprocessors and
DSPs
Custom USB Devices
Cameras
Desktop Routers
PLCs
Set-Top Boxes
PDAs
MP3 Players
Instrumentation
PART
TEMP RANGE
PIN-
PACKAGE
PACKAGE
CODE
M AX 3420E E C J
- 40°C to + 85°C
32 TQFP
7m m x 7m m x
1.4m m
C 32- 1
M AX 3420E E TG*
- 40°C to + 85°C
24 TQFN
4m m x 4m m x
0.8m m
T2444- 4
Ordering Information
*Future product—contact factory for availability.
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Inhaltsverzeichnis

Seite 1 - USB Peripheral Controller

General DescriptionThe MAX3420E contains the digital logic and analogcircuitry necessary to implement a full-speed USBperipheral compliant to USB spec

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MAX3420EUSB Peripheral Controllerwith SPI Interface10 ______________________________________________________________________________________Note 1: Pa

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MAX3420EUSB Peripheral Controllerwith SPI Interface______________________________________________________________________________________ 11Test Circu

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MAX3420EUSB Peripheral Controllerwith SPI Interface12 ______________________________________________________________________________________Typical Op

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(NOVBUSIRQ)) and disconnect the internal 1.5kΩpullup resistor. If the device using the MAX3420E isbus powered (through a +3.3V regulator connected toV

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MAX3420E(R17) register to make INT active high, and clear thePOSINT bit to make INT active low.GPIN3–GPIN0, GPOUT3–GPOUT0 and GPXThe MAX3420E has four

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In full-duplex mode (FDUPSPI=1), the MOSI and MISOpins are separate, and the MISO pin drives only when SSis low. In this mode, the first eight SCLK ed

Seite 8

MAX3420ESPI Half- and Full-Duplex OperationThe MAX3420E can be programmed to operate in half-duplex (a bidirectional data pin) or full-duplex (onedata

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(5) To write SPI data, the SPI master keeps its outputdriver on and clocks subsequent bytes into theMOSI pin. To read SPI data, after the eighth clock

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MAX3420Epre-shutdown tasks before it requests the MAX3420E toenter the power-down state by setting PWRDOWN = 1.Wakeup and USB ResumeThe MAX3420E may w

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MAX3420E in a Bus-Powered ApplicationFigure 16 depicts the MAX3420E in a peripheral devicethat is powered by VBUS. This configuration is advanta-geous

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The MAX3420E connects to any microprocessor using3 or 4 interface pins (Figure 1). On a simple micro-processor without SPI hardware, these can be bit-

Seite 13

MAX3420Ewhether the USB device is plugged in or not, it needssome way to detect a plug-in event. A comparatorinside the MAX3420E checks for a valid VB

Seite 14

capacitors connected to ground as close to the pins aspossible. D+, D-, and VBCOMP provide protection tothe following limits:• ±15kV using the Human B

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MAX3420EUSB Peripheral Controllerwith SPI Interface22 ______________________________________________________________________________________Package In

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MAX3420EUSB Peripheral Controllerwith SPI InterfaceMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied

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MAX3420EUSB Peripheral Controllerwith SPI Interface_______________________________________________________________________________________ 3Functional

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MAX3420EUSB Peripheral Controllerwith SPI Interface4 _______________________________________________________________________________________Pin Descri

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Register DescriptionThe SPI master controls the MAX3420E by reading andwriting 21 registers (Table 1). For a complete descrip-tion of register content

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MAX3420Emode, these status bits are accessed in the normalway, as register bits.The first five registers (R0–R4) access endpoint FIFOs.To access a FIF

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MAX3420EUSB Peripheral Controllerwith SPI Interface_______________________________________________________________________________________ 7TQFNMAX342

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MAX3420EUSB Peripheral Controllerwith SPI Interface8 _______________________________________________________________________________________ABSOLUTE M

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MAX3420EUSB Peripheral Controllerwith SPI Interface_______________________________________________________________________________________ 9ELECTRICAL

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