MAX9257/MAX9258
A GPIO can be programmed to drive an LVCMOS logic
level or to read a logic input. The register bit that sets
the output level when the GPIO is programmed as an
output stores the input level when the GPIO is pro-
grammed as an input.
Open-Drain Outputs (LOCK,
ERROR
)
LOCK and ERROR are open-drain outputs that require
a pullup resistor to an external supply. ERROR asserts
low when an error occurs and LOCK is high impedance
when the MAX9258 is locked to the MAX9257 and
remains high under the locked condition. When the
devices are in shutdown, the channel is not locked and
LOCK goes high impedance, is pulled high, and should
be ignored. ERROR is high impedance at shutdown
and remains high. In choosing pullup resistors, there is
a tradeoff between power dissipation and speed; 10kΩ
pullup should be sufficient.
26 ______________________________________________________________________________________
Fully Programmable Serializer/Deserializer
with UART/I
2
C Control Channel
SERIAL-WORD
LENGTH
SRATE PRATE
PCLK RANGE
(MHz)
MODULATION RATE f
SSM
RANGE (kHz)
11 11 40–70 PCLK/2728 14.7 to 25.7
11 10 33.3–40 PCLK/1736 19.2 to 23.0
10 10 20–33.3 PCLK/1612 12.4 to 20.7
10 01 16.6–20 PCLK/992 16.7 to 20.2
01 01 10–16.6 PCLK/1116 9.0 to 14.9
01 00 8.3–10 PCLK/744 11.2 to 13.4
12
00 00 5–8.3 PCLK/868 5.8 to 9.6
11 11 40–60 PCLK/2304 17.4 to 26.0
11 10 28.6–40 PCLK/1728 16.6 to 23.1
10 10 20–28.6 PCLK/1440 13.9 to 19.9
10 01 14.3–20 PCLK/1008 14.2 to 19.8
01 01 10–14.3 PCLK/1008 9.9 to 14.2
01 00 7.1–10 PCLK/720 9.9 to 13.9
14
00 00 5–7.1 PCLK/720 6.9 to 9.9
11 11 40–52.5 PCLK/1968 20.3 to 26.7
11 10 25–40 PCLK/1640 15.2 to 24.4
10 10 20–25 PCLK/1312 15.2 to 19.1
10 01 12.5–20 PCLK/984 12.7 to 20.3
01 01 10–12.5 PCLK/820 12.2 to 15.2
01 00 6.25–10 PCLK/656 9.5 to 15.2
16
00 00 5–6.25 PCLK/656 7.6 to 9.5
11 11 40–46.6 PCLK/1840 21.7 to 25.3
11 10 22.2–40 PCLK/1472 15.1 to 27.2
10 10 20–22.2 PCLK/1104 18.1 to 20.1
10 01 11.1–20 PCLK/920 12.1 to 21.7
01 01 10–11.1 PCLK/736 13.6 to 15.1
01 00 5.6–10 PCLK/736 7.6 to 13.6
18
00 00 5–5.6 PCLK/552 9.1 to 10.1
11 11 40–42 PCLK/1632 24.5 to 25.7
11 10 20–40 PCLK/1632 12.3 to 24.5
10 01 10–20 PCLK/1020 9.8 to 19.6
20
01 00 5–10 PCLK/816 6.1 to 12.3
Table 20. MAX9257 Modulation Rate
(1 Seiten)
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