MAX9257/MAX9258
register REG2 for both the MAX9257 and the MAX9258.
The four bits of REG2[7:4] select the divide ratio (STODIV)
for the STO clock as a function of the pixel clock (Table
24). The timeout period is determined by counter bits
REG2[3:0] that increment once every STO clock period.
Write to REG2[3:0] to determine the counter end time.
The STO counter counts to the programmed STOCNT +
1. The ECU must begin communicating before STO times
out, otherwise, the control channel closes (Figure 22). The
STO timeout period is given by:
For example:
If the pixel clock frequency is set to 16MHz, STODIV is
set to 1010 (STODIV = 1024), and STOCNT is set to
1001 (STOCNT = 9), the STO timer counts with
15.625kHz STO clock (16MHz/1024) internally until it
reaches 10 and timer expires. The t
STO
is equal to t
T
x
1024 x 10 = 640µs.
The default value for STODIV is 1024 while the default
value for STOCNT is 0. That means the STO timeout
period is equal 1024 pixel clock cycles. Activity from
the ECU on the control channel shuts off the STO timer
and starts the ETO timer.
ETO Timer
The ETO (end timeout) timer closes the control channel
if the ECU stops communicating for the ETO timeout
period. Configure register REG3[7:4] for both the
MAX9257 and the MAX9258 to select the divide ratio
(ETODIV) for the ETO clock as a function of the pixel
clock (Table 25). The timeout period is determined by
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