
80
3621A–MICRO–6/06
AT89LP216 [Preliminary]
Figure 24-6. Shift Register Mode Timing Waveform
24.6 Test Conditions
24.6.1 AC Testing Input/Output Waveform
(1)
Note: 1. AC Inputs during testing are driven at V
CC
- 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at
V
IH
min. for a logic “1” and V
IL
max. for a logic “0”.
24.6.2 Float Waveform
(1)
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when 100 mV change from the loaded V
OH
/V
OL
level occurs.
24.5 Serial Port Timing: Shift Register Mode
The values in this table are valid for V
CC
= 2.4V to 5.5V and Load Capacitance = 80 pF.
Symbol Parameter
Variable Oscillator
UnitsMin Max
t
XLXL
Serial Port Clock Cycle Time 2t
CLCL
-15 µs
t
QVXH
Output Data Setup to Clock Rising Edge t
CLCL
-15 ns
t
XHQX
Output Data Hold after Clock Rising Edge t
CLCL
-15 ns
t
XHDX
Input Data Hold after Clock Rising Edge 0 ns
t
XHDV
Input Data Valid to Clock Rising Edge 15 ns
01234567
ValidValidValidValid Valid Valid Valid Valid
Clock
Write to SBUF
Output Data
Clear RI
Input Data
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