Rainbow-electronics AT89LP216 Bedienungsanleitung

Features• 8-bit Microcontroller Compatible with MCS®51 Products• Enhanced 8051 Architecture– Single-clock Cycle per Byte Fetch– Up to 20 MIPS Throughp

103621A–MICRO–6/06AT89LP216 [Preliminary]Figure 8-3. Two-cycle ALU Operation (Example: ADD A, #data)8.1 Restrictions on Certain InstructionsThe AT89LP

113621A–MICRO–6/06AT89LP216 [Preliminary]9. System ClockThe system clock is generated directly from one of three selectable clock sources. The threeso

123621A–MICRO–6/06AT89LP216 [Preliminary] 10. ResetDuring reset, all I/O Registers are set to their initial values, the port pins are tristated, and t

133621A–MICRO–6/06AT89LP216 [Preliminary]Figure 10-1. Power-on Reset Sequence (BOD Disabled)If the Brown-out Detector (BOD) is also enabled, the start

143621A–MICRO–6/06AT89LP216 [Preliminary]10.2 Brown-out ResetThe AT89LP216 has an on-chip Brown-out Detection (BOD) circuit for monitoring the VCC lev

153621A–MICRO–6/06AT89LP216 [Preliminary]10.4 Watchdog ResetWhen the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cyc

163621A–MICRO–6/06AT89LP216 [Preliminary]When terminating Power-down by an interrupt, two different wake-up modes are available.When PWDEX in PCON is

173621A–MICRO–6/06AT89LP216 [Preliminary]Figure 11-3. Reset Recovery from Power-down. Table 11-1. PCON – Power Control RegisterPCON = 87H Reset Value

183621A–MICRO–6/06AT89LP216 [Preliminary]12. InterruptsThe AT89LP216 provides 7 interrupt sources: two external interrupts, two timer interrupts, aser

193621A–MICRO–6/06AT89LP216 [Preliminary]12.1 Interrupt Response TimeThe interrupt flags may be set by their hardware in any clock cycle. The interrup

23621A–MICRO–6/06AT89LP216 [Preliminary]have bytes to execute, and most of the remaining instructions require only one additional clock.The enhanced C

203621A–MICRO–6/06AT89LP216 [Preliminary]Figure 12-1. Minimum Interrupt Response TimeFigure 12-2. Maximum Interrupt Response Time.Clock CyclesINT0IE01

213621A–MICRO–6/06AT89LP216 [Preliminary]Table 12-3. IP – Interrupt Priority RegisterIP = B8H Reset Value = X000 0000BBit Addressable––PGP PS PT1 PX1

223621A–MICRO–6/06AT89LP216 [Preliminary]13. I/O PortsThe AT89LP216 can be configured for between 9 and 12 I/O pins. The exact number of I/O pinsavail

233621A–MICRO–6/06AT89LP216 [Preliminary]13.1.1 Quasi-bidirectional OutputPort pins in quasi-bidirectional output mode function similar to standard 80

243621A–MICRO–6/06AT89LP216 [Preliminary]13.1.2 Input-only ModeThe input only port configuration is shown in Figure 13-2. The output drivers are trist

253621A–MICRO–6/06AT89LP216 [Preliminary]Figure 13-5. Push-pull Output13.2 Port 1 Analog FunctionsThe AT89LP216 incorporates an analog comparator. In

263621A–MICRO–6/06AT89LP216 [Preliminary]13.4 Port Alternate FunctionsMost general-purpose digital I/O pins of the AT89LP216 share functionality with

273621A–MICRO–6/06AT89LP216 [Preliminary]14. Enhanced Timer/CountersThe AT89LP216 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a Ti

283621A–MICRO–6/06AT89LP216 [Preliminary]Figure 14-1. Timer/Counter 1 Mode 0: Variable Width CounterMode 0 operation is the same for Timer 0 as for Ti

293621A–MICRO–6/06AT89LP216 [Preliminary]14.3 Mode 2 – 8-bit Auto-Reload Timer/CounterMode 2 configures the Timer register as an 8-bit Counter (TL1) w

33621A–MICRO–6/06AT89LP216 [Preliminary]3. Pin DescriptionTable 3-1. AT89LP216 Pin DescriptionPin Symbol Type Description1P1.5I/OI/OIP1.5: User-config

303621A–MICRO–6/06AT89LP216 [Preliminary].Table 14-1. TCON – Timer/Counter Control RegisterTCON = 88H Reset Value = 0000 0000BBit AddressableTF1 TR1 T

313621A–MICRO–6/06AT89LP216 [Preliminary]Table 14-2. TMOD: Timer/Counter Mode Control RegisterTMOD = 88H Reset Value = 0000 0000B Not Bit AddressableG

323621A–MICRO–6/06AT89LP216 [Preliminary].14.5 Pulse Width ModulationOn the AT89LP216, Timer 0 and Timer 1 may be independently configured as 8-bit as

333621A–MICRO–6/06AT89LP216 [Preliminary]14.5.1 Mode 0 – 8-bit PWM with 8-bit Logarithmic PrescalerIn Mode 0, TLx acts as a logarithmic prescaler driv

343621A–MICRO–6/06AT89LP216 [Preliminary]Figure 14-7. Timer/Counter 1 PWM Mode 114.5.3 Mode 2 – 8-bit Frequency GeneratorTimer 0 in PWM Mode 2 functio

353621A–MICRO–6/06AT89LP216 [Preliminary]14.5.4 Mode 3 – Split 8-bit PWMTimer 1 in PWM Mode 3 simply holds its count. The effect is the same as settin

363621A–MICRO–6/06AT89LP216 [Preliminary]15. External InterruptsWhen the AT89LP216 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 ma

373621A–MICRO–6/06AT89LP216 [Preliminary]..Table 16-2. GPLS – General-purpose Interrupt Level Select RegisterGPLS = 9BH Reset Value = 0000 0000BNot Bi

383621A–MICRO–6/06AT89LP216 [Preliminary]17. Serial InterfaceThe serial interface on the AT89LP216 implements a Universal Asynchronous Receiver/Trans-

393621A–MICRO–6/06AT89LP216 [Preliminary]bit and prepares to receive the data bytes that follows. The slaves that are not addressed settheir SM2 bits

43621A–MICRO–6/06AT89LP216 [Preliminary]4. Block DiagramFigure 4-1. AT89LP216 Block Diagram5. Comparison to Standard 8051The AT89LP216 is part of a fa

403621A–MICRO–6/06AT89LP216 [Preliminary]17.2 Baud RatesThe baud rate in Mode 0 is fixed as shown in the following equation:The baud rate in Mode 2 de

413621A–MICRO–6/06AT89LP216 [Preliminary]Table 17-2 lists commonly used baud rates and how they can be obtained from Timer 1.17.3 More About Mode 0Ser

423621A–MICRO–6/06AT89LP216 [Preliminary]Figure 17-1. Serial Port Mode 0INTERNAL BUS1/2 foscINTERNAL BUSTXD (SHIFT CLOCK)RXD (DATA OUT)TXD (SHIFT CLOC

433621A–MICRO–6/06AT89LP216 [Preliminary]17.4 More About Mode 1Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 d

443621A–MICRO–6/06AT89LP216 [Preliminary]Figure 17-2. Serial Port Mode 1 TXCLOCKWRITE TO SBUFINTERNAL BUSREADSBUFLOADSBUFSBUFSHIFTINPUT SHIFT REG.(9 B

453621A–MICRO–6/06AT89LP216 [Preliminary]17.5 More About Modes 2 and 3Eleven bits are transmitted (through TXD), or received (through RXD): a start bi

463621A–MICRO–6/06AT89LP216 [Preliminary]Figure 17-3. Serial Port Mode 2SMOD1 1SMOD1 0INTERNAL BUSINTERNAL BUSCPU CLOCK

473621A–MICRO–6/06AT89LP216 [Preliminary]Figure 17-4. Serial Port Mode 3 TXCLOCKWRITE TO SBUFSENDDATASHIFTTXDSTOP BIT GENTID0 D1 D2 D3 D4 D5 D6 D7 TB8

483621A–MICRO–6/06AT89LP216 [Preliminary]17.6 Framing Error DetectionIn addition to all of its usual modes, the UART can perform framing error detecti

493621A–MICRO–6/06AT89LP216 [Preliminary]In a more complex system, the following could be used to select slaves 1 and 2 while excludingslave 0: Slave

53621A–MICRO–6/06AT89LP216 [Preliminary]5.3 Interrupt HandlingThe interrupt controller polls the interrupt flags during the last clock cycle of any in

503621A–MICRO–6/06AT89LP216 [Preliminary]The interconnection between master and slave CPUs with SPI is shown in Figure 18-1. The fourpins in the inter

513621A–MICRO–6/06AT89LP216 [Preliminary]Notes: 1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then

523621A–MICRO–6/06AT89LP216 [Preliminary]Table 18-3. SPSR – SPI Status RegisterSPSR Address = E8H Reset Value = 000X X000BNot Bit AddressableSPIF WCOL

533621A–MICRO–6/06AT89LP216 [Preliminary]Figure 18-2. SPI Shift Register DiagramFigure 18-3. SPI Block Diagram2:1MUX2:1MUXSerial Master Serial SlaveLA

543621A–MICRO–6/06AT89LP216 [Preliminary]The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =baud rate) bits in SPCR

553621A–MICRO–6/06AT89LP216 [Preliminary]19. Analog ComparatorA single analog comparator is provided on the AT89LP216. The analog comparator has the f

563621A–MICRO–6/06AT89LP216 [Preliminary]Note: 1. Debouncing modes require the use of Timer 1 to generate the sampling delay.Table 19-1. ACSR – Analog

573621A–MICRO–6/06AT89LP216 [Preliminary]20. Programmable Watchdog TimerThe programmable Watchdog Timer (WDT) protects the system from incorrect execu

583621A–MICRO–6/06AT89LP216 [Preliminary]20.1 Software ResetA Software Reset of the AT89LP216 is accomplished by writing the software reset sequence5A

593621A–MICRO–6/06AT89LP216 [Preliminary]21. Instruction Set SummaryThe AT89LP216 is fully binary compatible with the MCS-51 instruction set. The diff

63621A–MICRO–6/06AT89LP216 [Preliminary]5.8 ResetThe RST pin of the AT89LP216 is active-low as compared with the active high reset in the stan-dard 80

603621A–MICRO–6/06AT89LP216 [Preliminary]Arithmetic BytesClock CyclesHex Code8051 AT89LPINC DPTR 1 24 2 A3MUL AB 1 48 2 A4DIV AB 1 48 4 84DA A 1 12 1

613621A–MICRO–6/06AT89LP216 [Preliminary]Data Transfer BytesClock CyclesHex Code8051 AT89LPMOV A, Rn 1 12 1 E8-EFMOV A, direct 2 12 2 E5MOV A, @Ri 1 1

623621A–MICRO–6/06AT89LP216 [Preliminary]Note: 1. This escaped instruction is an extension to the instruction set.Bit Operations BytesClock CyclesHex

633621A–MICRO–6/06AT89LP216 [Preliminary]22. On-Chip Debug SystemThe AT89LP216 On-Chip Debug (OCD) System uses a two-wire serial interface to control

643621A–MICRO–6/06AT89LP216 [Preliminary]22.2 Software BreakpointsThe AT89LP216 microcontroller includes a BREAK instruction for implementing program

653621A–MICRO–6/06AT89LP216 [Preliminary]23. Programming the Flash MemoryThe Atmel AT89LP216 microcontroller features 2K bytes of on-chip In-System Pr

663621A–MICRO–6/06AT89LP216 [Preliminary]The In-System Programming Interface is the only means of externally programming theAT89LP216 microcontroller.

673621A–MICRO–6/06AT89LP216 [Preliminary]Figure 23-2. AT89LP216 Memory Organization23.3 Command FormatProgramming commands consist of an opcode byte,

683621A–MICRO–6/06AT89LP216 [Preliminary]Figure 23-3. Command Sequence Flow ChartFigure 23-4. ISP Command PacketInput Preamble 2(55h)Input OpcodeInput

693621A–MICRO–6/06AT89LP216 [Preliminary]Notes: 1. Program Enable must be the first command issued after entering into programming mode.2. Any number

73621A–MICRO–6/06AT89LP216 [Preliminary]The Atmel Signature Array is initialized with the Device ID in the factory. The User SignatureArray is availab

703621A–MICRO–6/06AT89LP216 [Preliminary]23.4 Status RegisterThe current state of the memory may be accessed by reading the status register. The statu

713621A–MICRO–6/06AT89LP216 [Preliminary]23.7 User Configuration FusesThe AT89LP216 includes 19 user fuses for configuration of the device. Each fuse

723621A–MICRO–6/06AT89LP216 [Preliminary]23.8 Programming Interface TimingThis section details general system timing sequences and constraints for ent

733621A–MICRO–6/06AT89LP216 [Preliminary]23.8.3 ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device

743621A–MICRO–6/06AT89LP216 [Preliminary]23.8.5 Serial Peripheral InterfaceThe Serial Peripheral Interface (SPI) is a byte-oriented full-duplex synchr

753621A–MICRO–6/06AT89LP216 [Preliminary]23.8.6 Timing ParametersThe timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Fig

763621A–MICRO–6/06AT89LP216 [Preliminary]24. Electrical CharacteristicsNotes: 1. Under steady state (non-transient) conditions, IOL must be externally

773621A–MICRO–6/06AT89LP216 [Preliminary]24.3 Serial Peripheral Interface Timing Table 24-1. SPI Master CharacteristicsSymbol Parameter Min Max Unitst

783621A–MICRO–6/06AT89LP216 [Preliminary]Figure 24-1. SPI Master Timing (CPHA = 0)Figure 24-2. SPI Slave Timing (CPHA = 0)Figure 24-3. SPI Master Timi

793621A–MICRO–6/06AT89LP216 [Preliminary]Figure 24-4. SPI Slave Timing (CPHA = 1)24.4 External Clock DriveFigure 24-5. External Clock Drive Waveform S

83621A–MICRO–6/06AT89LP216 [Preliminary]7. Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space

803621A–MICRO–6/06AT89LP216 [Preliminary] Figure 24-6. Shift Register Mode Timing Waveform24.6 Test Conditions24.6.1 AC Testing Input/Output Waveform(

813621A–MICRO–6/06AT89LP216 [Preliminary]24.6.3 ICC Test Condition, Active Mode, All Other Pins are Disconnected24.6.4 ICC Test Condition, Idle Mode,

823621A–MICRO–6/06AT89LP216 [Preliminary]25. Ordering Information 25.1 Standard PackageSpeed (MHz)PowerSupply Ordering Code Package Operation Range20

833621A–MICRO–6/06AT89LP216 [Preliminary]26. Packaging Information26.1 16P3 – PDIP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 16

843621A–MICRO–6/06AT89LP216 [Preliminary]26.2 16S2 – SOIC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 16S2, 16-lead, 0.300" Wide

853621A–MICRO–6/06AT89LP216 [Preliminary]26.3 16X – TSSOPTITLEDRAWING NO.RREV. 2325 Orchard Parkway San Jose, CA 9513111/11/0516X, 16-lead, 4.4 m

863621A–MICRO–6/06AT89LP216 [Preliminary]27. Revision History Revision No. HistoryRevision A – June 2006 • Initial Release

i3621A–MICRO–6/06AT89LP216 [Preliminary]Table of Contents1. Description ...

ii3621A–MICRO–6/06AT89LP216 [Preliminary]Table of Contents (Continued)12. Interrupts ...

iii3621A–MICRO–6/06AT89LP216 [Preliminary]Table of Contents (Continued)23. Programming the Flash Memory ...

93621A–MICRO–6/06AT89LP216 [Preliminary]8. Enhanced CPUThe AT89LP216 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard8051 de

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