Rainbow-electronics ATmega64C1 Bedienungsanleitung

Features• High Performance, Low Power AVR ® 8-bit Microcontroller• Advanced RISC Architecture– 131 Powerful Instructions - Most Single Clock Cycle Exe

107647A–AVR–02/08ATmega32/64/M1/C12.3.3 Port B (PB7..PB0)Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

1007647A–AVR–02/08ATmega32/64/M1/C112.8 8-bit Timer/Counter Register Description12.8.1 Timer/Counter Control Register A – TCCR0A• Bits 7:6 – COM0A1:0:

1017647A–AVR–02/08ATmega32/64/M1/C1Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-pare Match is ignored

1027647A–AVR–02/08ATmega32/64/M1/C1Table 12-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-rect PWM mode.Note: 1. A

1037647A–AVR–02/08ATmega32/64/M1/C1• Bit 7 – FOC0A: Force Output Compare AThe FOC0A bit is only active when the WGM bits specify a non-PWM mode.Howeve

1047647A–AVR–02/08ATmega32/64/M1/C112.8.3 Timer/Counter Register – TCNT0The Timer/Counter Register gives direct access, both for read and write operat

1057647A–AVR–02/08ATmega32/64/M1/C1overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-rupt Flag Register –

1067647A–AVR–02/08ATmega32/64/M1/C113. 16-bit Timer/Counter1 with PWMThe 16-bit Timer/Counter unit allows accurate program execution timing (event man

1077647A–AVR–02/08ATmega32/64/M1/C1Figure 13-1. 16-bit Timer/Counter Block Diagram(1)Note: 1. Refer toTable on page 5 for Timer/Counter1 pin placemen

1087647A–AVR–02/08ATmega32/64/M1/C1The Input Capture Register can capture the Timer/Counter value at a given external (edge trig-gered) event on eithe

1097647A–AVR–02/08ATmega32/64/M1/C1Note: 1. The example code assumes that the part specific header file is included.For I/O Registers located in exten

117647A–AVR–02/08ATmega32/64/M1/C1The various special features of Port E are elaborated in “Alternate Functions of Port E” on page77 and “Clock System

1107647A–AVR–02/08ATmega32/64/M1/C1The following code examples show how to do an atomic read of the TCNTn Register contents.Reading any of the OCRnx o

1117647A–AVR–02/08ATmega32/64/M1/C1The following code examples show how to do an atomic write of the TCNTn Register contents.Writing any of the OCRnx

1127647A–AVR–02/08ATmega32/64/M1/C113.4 Counter UnitThe main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.F

1137647A–AVR–02/08ATmega32/64/M1/C113.5 Input Capture UnitThe Timer/Counter incorporates an Input Capture unit that can capture external events and gi

1147647A–AVR–02/08ATmega32/64/M1/C1For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”on page 108.The ICF

1157647A–AVR–02/08ATmega32/64/M1/C113.5.4 Using the Input Capture Unit as TCNT1 Retrigger InputTCNT1 counts from BOTTOM to TOP. The TOP value can be a

1167647A–AVR–02/08ATmega32/64/M1/C1double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-pare Register to either

1177647A–AVR–02/08ATmega32/64/M1/C1Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 13-5 shows a simplifiedschematic of the logic

1187647A–AVR–02/08ATmega32/64/M1/C1A change of the COMnx1:0 bits state will have effect at the first compare match after the bits arewritten. For non-

1197647A–AVR–02/08ATmega32/64/M1/C1Figure 13-6. CTC Mode, Timing DiagramAn interrupt can be generated at each time the counter value reaches the TOP v

127647A–AVR–02/08ATmega32/64/M1/C13. AVR CPU Core3.1 IntroductionThis section discusses the AVR core architecture in general. The main function of the

1207647A–AVR–02/08ATmega32/64/M1/C1imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can becalculated by using the foll

1217647A–AVR–02/08ATmega32/64/M1/C1Using the ICRn Register for defining TOP works well when using fixed TOP values. By usingICRn, the OCRnA Register i

1227647A–AVR–02/08ATmega32/64/M1/C1TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clockcycle. The timing diag

1237647A–AVR–02/08ATmega32/64/M1/C1actual OCnx value will only be visible on the port pin if the data direction for the port pin is set asoutput (DDR_

1247647A–AVR–02/08ATmega32/64/M1/C1Figure 13-9. Phase and Frequency Correct PWM Mode, Timing DiagramThe Timer/Counter Overflow Flag (TOVn) is set at t

1257647A–AVR–02/08ATmega32/64/M1/C1The extreme values for the OCRnx Register represents special cases when generating a PWMwaveform output in the phas

1267647A–AVR–02/08ATmega32/64/M1/C1Figure 13-12. Timer/Counter Timing Diagram, no PrescalingFigure 13-13 shows the same timing data, but with the pres

1277647A–AVR–02/08ATmega32/64/M1/C1I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-ing to the OCnA or

1287647A–AVR–02/08ATmega32/64/M1/C1Note: 1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. See“Phase Correct PWM Mode” on

1297647A–AVR–02/08ATmega32/64/M1/C1Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the function

137647A–AVR–02/08ATmega32/64/M1/C1The fast-access Register File contains 32 x 8-bit general purpose working registers with a singleclock cycle access

1307647A–AVR–02/08ATmega32/64/M1/C1If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock thecounter even if the

1317647A–AVR–02/08ATmega32/64/M1/C1The Output Compare Registers contain a 16-bit value that is continuously compared with thecounter value (TCNTn). A

1327647A–AVR–02/08ATmega32/64/M1/C113.10.7 Input Capture Register 1 – ICR1H and ICR1LThe Input Capture is updated with the counter (TCNTn) value each

1337647A–AVR–02/08ATmega32/64/M1/C113.10.9 Timer/Counter1 Interrupt Flag Register – TIFR1• Bit 7, 6 – Res: Reserved BitsThese bits are unused bits in

1347647A–AVR–02/08ATmega32/64/M1/C114. Power Stage Controller – (PSC) (only ATmega32/64M1)The Power Stage Controller is a high performance waveform co

1357647A–AVR–02/08ATmega32/64/M1/C114.4 PSC DescriptionFigure 14-1. Power Stage Controller Block DiagramDATABUSPOCR_RB=PSC CounterWaveformGenerator BP

1367647A–AVR–02/08ATmega32/64/M1/C1The PSC is based on the use of a free-running 12-bit counter (PSC counter). This counter isable to count up to a to

1377647A–AVR–02/08ATmega32/64/M1/C1Figure 14-3. Cycle Presentation in Centered ModeFigure 14-2 and Figure 14-3 graphically illustrate the values held

1387647A–AVR–02/08ATmega32/64/M1/C1Figure 14-4. PSCOUTnA & PSCOUTnB Basic Waveforms in One Ramp modeOn-Time A = (POCRnRAH/L - POCRnSAH/L) * 1/Fclk

1397647A–AVR–02/08ATmega32/64/M1/C1Figure 14-5. Controlled Start and Stop Mechanism in One-Ramp ModeNote: See “PSC Control Register – PCTL” on page 15

147647A–AVR–02/08ATmega32/64/M1/C13.4 Status RegisterThe Status Register contains information about the result of the most recently executed arith-met

1407647A–AVR–02/08ATmega32/64/M1/C1PSC Cycle = 2 * (POCRnRBH/L + 1) * 1/FclkpscNote: Minimal value for PSC Cycle = 2 * 1/FclkpscNote that in center al

1417647A–AVR–02/08ATmega32/64/M1/C114.6.1 Value Update SynchronizationNew timing values or PSC output configuration can be written during the PSC cycl

1427647A–AVR–02/08ATmega32/64/M1/C114.8 Signal DescriptionFigure 14-9. PSC External Block View14.8.1 Input DescriptionTable 14-1. Internal InputsPOCRR

1437647A–AVR–02/08ATmega32/64/M1/C1Table 14-2. Block Inputs14.8.2 Output DescriptionTable 14-3. Block OutputsTable 14-4. Internal OutputsNote: 1. See

1447647A–AVR–02/08ATmega32/64/M1/C114.9 PSC InputFor detailed information on the PSC, please refer to Application Note ‘AVR138: PSC Cookbook’,availabl

1457647A–AVR–02/08ATmega32/64/M1/C1PSC Input Filterring14.9.1.2 Signal PolarityOne can select the active edge (edge modes) or the active level (level

1467647A–AVR–02/08ATmega32/64/M1/C1Figure 14-11. PSC behaviour versus PSCn Input in Mode 001b to 10xbFigure 14-12. PSC behaviour versus PSCn Input A o

1477647A–AVR–02/08ATmega32/64/M1/C1Used in Fault mode 7, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0or on On-Time1/Dead-Time

1487647A–AVR–02/08ATmega32/64/M1/C114.12 Analog SynchronizationEach PSC module generates a signal to synchronize the ADC sample and hold; synchronisat

1497647A–AVR–02/08ATmega32/64/M1/C114.15 InterruptsThis section describes the specifics of the interrupt handling as performed inATmega32/64/M1/C1.14.

157647A–AVR–02/08ATmega32/64/M1/C1• Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction

1507647A–AVR–02/08ATmega32/64/M1/C1• Bit 6 – not usenot use• Bit 5 – POEN2B: PSC Output 2B EnableWhen this bit is clear, I/O pin affected to PSCOUT2B

1517647A–AVR–02/08ATmega32/64/M1/C1• Bit 5:4 – PSYNC21:0: Synchronization Out for ADC SelectionSelect the polarity and signal source for generating a

1527647A–AVR–02/08ATmega32/64/M1/C114.16.5 PSCOutput Compare SB Register – POCRnSBH and POCRnSBL14.16.6 PSC Output Compare RB Register – POCR_RBH and

1537647A–AVR–02/08ATmega32/64/M1/C1• Bit 3 – POPB: PSC B Output PolarityIf this bit is cleared, the PSC outputs B are active Low.If this bit is set, t

1547647A–AVR–02/08ATmega32/64/M1/C114.16.9 PSC Module n Input Control Register – PMICnThe Input Control Registers are used to configure the 2 PSC’s Re

1557647A–AVR–02/08ATmega32/64/M1/C114.16.10 PSC Interrupt Mask Register – PIM• Bit 7:4 – not usenot use.• Bit 3 – PEVE2 : PSC External Event 2 Interru

1567647A–AVR–02/08ATmega32/64/M1/C1• Bit 2 – PEV1 : PSC External Event 1 InterruptThis bit is set by hardware when an external event which can generat

1577647A–AVR–02/08ATmega32/64/M1/C115. Serial Peripheral Interface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data trans

1587647A–AVR–02/08ATmega32/64/M1/C1the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-ter to Slave on the

1597647A–AVR–02/08ATmega32/64/M1/C1Note: 1. See “Alternate Functions of Port B” on page 67 for a detailed description of how to define thedirection of

167647A–AVR–02/08ATmega32/64/M1/C1Figure 3-3. The X-, Y-, and Z-registersIn the different addressing modes these address registers have functions as f

1607647A–AVR–02/08ATmega32/64/M1/C1Note: 1. The example code assumes that the part specific header file is included.The following code examples show h

1617647A–AVR–02/08ATmega32/64/M1/C1Note: 1. The example code assumes that the part specific header file is included.Assembly Code Example(1)SPI_SlaveI

1627647A–AVR–02/08ATmega32/64/M1/C115.2 SS Pin Functionality15.2.1 Slave ModeWhen the SPI is configured as a Slave, the Slave Select (SS) pin is alway

1637647A–AVR–02/08ATmega32/64/M1/C115.2.4 SPI Control Register – SPCR• Bit 7 – SPIE: SPI Interrupt EnableThis bit causes the SPI interrupt to be execu

1647647A–AVR–02/08ATmega32/64/M1/C1These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 haveno effect on the Slave.

1657647A–AVR–02/08ATmega32/64/M1/C115.2.6 SPI Data Register – SPDR• Bits 7:0 - SPD7:0: SPI DataThe SPI Data Register is a read/write register used for

1667647A–AVR–02/08ATmega32/64/M1/C1Figure 15-4. SPI Transfer Format with CPHA = 1SCK (CPOL = 0)mode 1SAMPLE IMOSI/MISOCHANGE 0MOSI PINCHANGE 0MISO PIN

1677647A–AVR–02/08ATmega32/64/M1/C116. Controller Area Network - CANThe Controller Area Network (CAN) protocol is a real-time, serial, broadcast proto

1687647A–AVR–02/08ATmega32/64/M1/C1by which the dominant state overwrites the recessive state. The competition for bus allocation islost by all nodes

1697647A–AVR–02/08ATmega32/64/M1/C116.2.2.2 CAN Extended FrameFigure 16-2. CAN Extended FramesA message in the CAN extended frame format is likely the

177647A–AVR–02/08ATmega32/64/M1/C1Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Har-vard architecture an

1707647A–AVR–02/08ATmega32/64/M1/C1Figure 16-3. CAN Bit Construction16.2.3.2 Synchronization SegmentThe first segment is used to synchronize the vario

1717647A–AVR–02/08ATmega32/64/M1/C1The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN.Since Phase Segment 2 a

1727647A–AVR–02/08ATmega32/64/M1/C1Figure 16-4. Bus Arbitration16.2.5 ErrorsThe CAN protocol signals any errors immediately as they occur. Three error

1737647A–AVR–02/08ATmega32/64/M1/C116.3 CAN ControllerThe CAN controller implemented into ATmega32/64/M1/C1 offers V2.0B Active.This full-CAN controll

1747647A–AVR–02/08ATmega32/64/M1/C116.4 CAN Channel16.4.1 ConfigurationThe CAN channel can be in:• Enabled modeIn this mode:– the CAN channel (interna

1757647A–AVR–02/08ATmega32/64/M1/C1The total number of TQ in a bit time has to be programmed at least from 8 to 25.Figure 16-7. Sample and Transmissio

1767647A–AVR–02/08ATmega32/64/M1/C15. Tsjw = (1 to 4) x Tscl = (SJW[1..0]+ 1) x TsclNotes: 1. The total number of Tscl (Time Quanta) in a bit time mus

1777647A–AVR–02/08ATmega32/64/M1/C116.5.2 Operating ModesThere is no default mode after RESET.Every MOb has its own fields to control the operating mo

1787647A–AVR–02/08ATmega32/64/M1/C12. The MOb is ready to receive a data or a remote frame when the MOb configuration is set (CONMOB).3. When a frame

1797647A–AVR–02/08ATmega32/64/M1/C116.5.3 Acceptance FilterUpon a reception hit (i.e., a good comparison between the ID + RTR + RBn + IDE received and

187647A–AVR–02/08ATmega32/64/M1/C1gramming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming ATmega32/64M1” on page 272.3

1807647A–AVR–02/08ATmega32/64/M1/C1The data index (INDX) is the address pointer to the required data byte. The data byte can beread or write. The data

1817647A–AVR–02/08ATmega32/64/M1/C116.7 Error Management16.7.1 Fault ConfinementThe CAN channel may be in one of the three following states:• Error ac

1827647A–AVR–02/08ATmega32/64/M1/C1– end-of-frame– error delimiter– overload delimiter• AERR: Acknowledgment error (Tx only). No detection of the domi

1837647A–AVR–02/08ATmega32/64/M1/C1Figure 16-14. CAN Controller Interrupt Structure16.8.2 Interrupt BehaviorWhen an interrupt occurs, an interrupt fla

1847647A–AVR–02/08ATmega32/64/M1/C116.9 CAN Register DescriptionFigure 16-15. Registers OrganizationGeneral ControlGeneral StatusGeneral InterruptBit

1857647A–AVR–02/08ATmega32/64/M1/C116.10 General CAN Registers16.10.1 CAN General Control Register - CANGCON• Bit 7 – ABRQ: Abort RequestThis is not a

1867647A–AVR–02/08ATmega32/64/M1/C1– 0 - standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (the

1877647A–AVR–02/08ATmega32/64/M1/C1• Bit 2 – ENFG: Enable FlagThis flag does not generate an interrupt.– 0 - CAN controller disable: because an enable

1887647A–AVR–02/08ATmega32/64/M1/C1– 0 - no interrupt.– 1 - burst receive interrupt: set when the frame buffer receive is completed.• Bit 3 – SERG: St

1897647A–AVR–02/08ATmega32/64/M1/C1– 0 - interrupt disabled.– 1- transmit interrupt enabled.• Bit 3 – ENERR: Enable MOb Errors Interrupt– 0 - interrup

197647A–AVR–02/08ATmega32/64/M1/C1When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-cuted before any pend

1907647A–AVR–02/08ATmega32/64/M1/C116.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1• Bits 5:0 - IEMOB5:0: Interrupt Enable by MOb– 0 - i

1917647A–AVR–02/08ATmega32/64/M1/C1The period of the CAN controller system clock Tscl is programmable and determines the individ-ual bit timing.If ‘BR

1927647A–AVR–02/08ATmega32/64/M1/C1• Bit 7– Reserved BitThis bit is reserved for future use. For compatibility with future devices, it must be written

1937647A–AVR–02/08ATmega32/64/M1/C116.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH• Bits 15:0 - TIMTTC15:0: TTC Timer CountCAN TTC timer counte

1947647A–AVR–02/08ATmega32/64/M1/C1• Bit 7:4 – MOBNB3:0: MOb NumberSelection of the MOb number, the available numbers are from 0 to 5.Note: MOBNB3 alw

1957647A–AVR–02/08ATmega32/64/M1/C1This flag can generate an interrupt. It must be cleared using a read-modify-write software routineon the whole CANS

1967647A–AVR–02/08ATmega32/64/M1/C1– 0 - reply not ready.– 1 - reply ready and valid.• Bit 4 – IDE: Identifier ExtensionIDE bit of the remote or data

1977647A–AVR–02/08ATmega32/64/M1/C1These bits are reserved for future use. For compatibility with future devices, they must be writtento zero when CAN

1987647A–AVR–02/08ATmega32/64/M1/C1V2.0 part BV2.0 part A• Bit 31:21 – IDMSK10:0: Identifier Mask– 0 - comparison true forced - See “Acceptance Filter

1997647A–AVR–02/08ATmega32/64/M1/C1– 0 - comparison true forced– 1 - bit comparison enabled.16.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH• Bi

27647A–AVR–02/08ATmega32/64/M1/C1– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)• Operating Voltage: 2.7V - 5.5V • Extended Operating Te

207647A–AVR–02/08ATmega32/64/M1/C14. MemoriesThis section describes the different memories in the ATmega32/64/M1/C1. The AVR architec-ture has two mai

2007647A–AVR–02/08ATmega32/64/M1/C1Table 16-2. Examples of CAN Baud Rate Settings for Commonly Frequencies fCLKIO(MHz)CANRate(Kbps)Description Segment

2017647A–AVR–02/08ATmega32/64/M1/C1Note: 1. See Section 16.4.3 “Baud Rate” on page 175.2. See Section • “Bit 0 – SMP: Sample Point(s)” on page 192 8.0

2027647A–AVR–02/08ATmega32/64/M1/C117. LIN / UART - Local Interconnect Network Controller or UARTThe LIN (Local Interconnect Network) is a serial comm

2037647A–AVR–02/08ATmega32/64/M1/C117.3 LIN Protocol17.3.1 Master and SlaveA LIN cluster consists of one master task and several slave tasks. A master

2047647A–AVR–02/08ATmega32/64/M1/C117.3.3 Data TransportTwo types of data may be transported in a frame; signals or diagnostic messages.• SignalsSigna

2057647A–AVR–02/08ATmega32/64/M1/C1forms to this perspective. The only link between the master task and the slave task will be at thecross-over point

2067647A–AVR–02/08ATmega32/64/M1/C117.4.3 LIN/UART Controller StructureFigure 17-4. LIN/UART Controller Block Diagram17.4.4 LIN/UART Command OverviewF

2077647A–AVR–02/08ATmega32/64/M1/C117.4.5 Enable / DisableSetting the LENA bit in LINCR register enables the LIN/UART controller. To disable theLIN/UA

2087647A–AVR–02/08ATmega32/64/M1/C117.4.6.2 Tx Header FunctionIn accordance with the LIN protocol, only the master task must enable this function. The

2097647A–AVR–02/08ATmega32/64/M1/C117.4.6.4 Handling Data of LIN responseA FIFO data buffer is used for data of the LIN response. After setting all pa

217647A–AVR–02/08ATmega32/64/M1/C1The ATmega32/64/M1/C1 is a complex microcontroller with more peripheral units than can besupported within the 64 loc

2107647A–AVR–02/08ATmega32/64/M1/C117.5 LIN / UART Description17.5.1 ResetThe AVR core reset logic signal also resets the LIN/UART controller. Another

2117647A–AVR–02/08ATmega32/64/M1/C1The LIN configuration is independent of the programmed LIN protocol.The listening mode connects the internal Tx LIN

2127647A–AVR–02/08ATmega32/64/M1/C1• “LIN Data Register” - LINDAT.The busy signal is not generated during a byte reception.17.5.6 Bit Timing17.5.6.1 B

2137647A–AVR–02/08ATmega32/64/M1/C1Figure 17-8. Handling LBT[5..0]17.5.7 Data LengthSection 17.4.6 “LIN Commands” on page 207 describes how to set or

2147647A–AVR–02/08ATmega32/64/M1/C117.5.7.3 Data Length in Rx ResponseFigure 17-9. LIN2.1 - Rx Response - No error • The user initializes LRXDL field

2157647A–AVR–02/08ATmega32/64/M1/C117.5.7.5 Data Length after ErrorFigure 17-11. Tx Response - Error Note: Information on response (ex: error on byte)

2167647A–AVR–02/08ATmega32/64/M1/C1ever, the LIN slave application has to solve this as:- known identifier (parity bits corrupted),- or corrupted iden

2177647A–AVR–02/08ATmega32/64/M1/C1BREAK/SYNC field sequence happens, the transfer in progress is aborted and the processing ofthe new frame starts.•

2187647A–AVR–02/08ATmega32/64/M1/C1Figure 17-13. LIN Interrupt Mapping 17.5.14 Message FilteringMessage filtering based upon the whole identifier is n

2197647A–AVR–02/08ATmega32/64/M1/C117.5.15.2 UART Data RegisterThe LINDAT register is the data register (no buffering - no FIFO). In write access, LIN

227647A–AVR–02/08ATmega32/64/M1/C1Figure 3. On-chip Data SRAM Access Cycles4.3 EEPROM Data MemoryThe ATmega32/64/M1/C1 contains 1024/2048 bytes of da

2207647A–AVR–02/08ATmega32/64/M1/C117.6 LIN / UART Register Description 17.6.1 LIN Control Register - LINCR • Bit 7 - LSWRES: Software Reset– 0 = No a

2217647A–AVR–02/08ATmega32/64/M1/C1– 10 = No Frame_Time_Out (listen mode “off” & CRC “on”),– 11 = Listening mode (CRC “on” & Frame_Time_Out “o

2227647A–AVR–02/08ATmega32/64/M1/C1– 1 = An error has occurred.The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR

2237647A–AVR–02/08ATmega32/64/M1/C1– 0 = Transmit performed interrupt masked,– 1 = Transmit performed interrupt enabled.• Bit 0 - LENRXOK: Enable Rece

2247647A–AVR–02/08ATmega32/64/M1/C1– 1 = Checksum error.This bit is cleared when LERR bit in LINSIR is cleared.• Bit 0 - LBERR: Bit Error Flag–0 = no

2257647A–AVR–02/08ATmega32/64/M1/C1In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max).In UART mode this field is u

2267647A–AVR–02/08ATmega32/64/M1/C117.6.9 LIN Data Buffer Selection Register - LINSEL• Bits 7:4 - Reserved BitsThese bits are reserved for future use.

2277647A–AVR–02/08ATmega32/64/M1/C118. Analog to Digital Converter - ADC18.1 Features• 10-bit Resolution• 0.5 LSB Integral Non-linearity• ± 2 LSB Abso

2287647A–AVR–02/08ATmega32/64/M1/C1Figure 18-1. Analog to Digital Converter Block SchematicMUX2 MUX1 MUX0MUX3REFS1 REFS0 ADLAR MUX4 ADPS2 ADPS1 ADPS0A

2297647A–AVR–02/08ATmega32/64/M1/C118.2 OperationThe ADC converts an analog input voltage to a 10-bit digital value through successive approxi-mation.

237647A–AVR–02/08ATmega32/64/M1/C14.3.2 The EEPROM Address Registers – EEARH and EEARL• Bits 15.10 – Reserved BitsThese bits are reserved bits in the

2307647A–AVR–02/08ATmega32/64/M1/C1Figure 18-2. ADC Auto Trigger LogicUsing the ADC Interrupt Flag as a trigger source makes the ADC start a new conve

2317647A–AVR–02/08ATmega32/64/M1/C1When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversionstarts at the following

2327647A–AVR–02/08ATmega32/64/M1/C1Figure 18-6. ADC Timing Diagram, Auto Triggered ConversionFigure 18-7. ADC Timing Diagram, Free Running Conversion1

2337647A–AVR–02/08ATmega32/64/M1/C1If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Specialcare must be take

2347647A–AVR–02/08ATmega32/64/M1/C1If differential channels are used, the selected reference should not be closer to AVCC than indi-cated in Table 25-

2357647A–AVR–02/08ATmega32/64/M1/C1Figure 18-8. Analog Input Circuitry18.6.2 Analog Noise Canceling TechniquesDigital circuitry inside and outside the

2367647A–AVR–02/08ATmega32/64/M1/C118.6.3 Offset Compensation SchemesThe gain stage has a built-in offset cancellation circuitry that nulls the offset

2377647A–AVR–02/08ATmega32/64/M1/C1Figure 18-11. Gain Error• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the m

2387647A–AVR–02/08ATmega32/64/M1/C1Figure 18-13. Differential Non-linearity (DNL)• Quantization Error: Due to the quantization of the input voltage in

2397647A–AVR–02/08ATmega32/64/M1/C1Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) isselected with a re

247647A–AVR–02/08ATmega32/64/M1/C1EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to0b00 unless the EEPROM

2407647A–AVR–02/08ATmega32/64/M1/C1– ADCL will thus read 0x00, and ADCH will read 0x9C.Writing zero to ADLAR right adjusts the result: ADCL = 0x70, AD

2417647A–AVR–02/08ATmega32/64/M1/C1The measured voltage has a linear relationship to the temperature as described in Table 18-3 onpage 241. The voltag

2427647A–AVR–02/08ATmega32/64/M1/C1• Bit 7, 6 – REFS1, 0: ADC Vref Selection BitsThese 2 bits determine the voltage reference for the ADC.The differen

2437647A–AVR–02/08ATmega32/64/M1/C1• Bit 4, 2, 1, 0 – MUX4, MUX3, MUX2, MUX1, MUX0: ADC Channel Selection BitsThese 4 bits determine which analog inpu

2447647A–AVR–02/08ATmega32/64/M1/C1• Bit 6– ADSC: ADC Start Conversion BitSet this bit to start a conversion in single conversion mode or to start the

2457647A–AVR–02/08ATmega32/64/M1/C1• Bit 6 – ISRCEN: Current Source EnableSet this bit to source a 100µA current to the AREF pin.Clear this bit to use

2467647A–AVR–02/08ATmega32/64/M1/C1Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust theresult thanks to

2477647A–AVR–02/08ATmega32/64/M1/C1analog signal is applied to an analog pin and the digital input from this pin is not needed, this bitshould be writ

2487647A–AVR–02/08ATmega32/64/M1/C1Figure 18-16. Amplifier synchronization timing diagramWith change on analog input signalValid sampleDelta V4th stab

2497647A–AVR–02/08ATmega32/64/M1/C1Figure 18-17. Amplifier synchronization timing diagramADSC is set when the amplifier output is changing due to the

257647A–AVR–02/08ATmega32/64/M1/C1When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-ware can poll this bit an

2507647A–AVR–02/08ATmega32/64/M1/C1Figure 18-18. Amplifiers block diagramAMP0TS1 AMP0TS0AMP0EN AMP0IS AMP0G1 AMP0G0AMP0CSR+-SAMPLINGAMP0+AMP0-Toward A

2517647A–AVR–02/08ATmega32/64/M1/C118.11 Amplifier Control RegistersThe configuration of the amplifiers are controlled via two dedicated registers AMP

2527647A–AVR–02/08ATmega32/64/M1/C1In accordance with the Table 18-9, these 3 bits select the event which will generate the clock forthe amplifier 0.

2537647A–AVR–02/08ATmega32/64/M1/C1Set this bit to connect the amplifier 1 to the comparator 1 positive input. In this configuration thecomparator clo

2547647A–AVR–02/08ATmega32/64/M1/C1To ensure an accurate result, after the gain value has been changed, the amplifier input needsto have a quite stabl

2557647A–AVR–02/08ATmega32/64/M1/C119. ISRC - Current Source19.1 Features• 100µA Constant current source• ± 2% Absolute AccuracyThe ATmega32/64/M1/C1

2567647A–AVR–02/08ATmega32/64/M1/C1ATmega32/64/M1/C1 proposes to have an external resistor used in conjunction with the CurrentSource. The device meas

2577647A–AVR–02/08ATmega32/64/M1/C119.2.2 Voltage Reference for External DevicesAn external resistor used in conjunction with the Current Source can b

2587647A–AVR–02/08ATmega32/64/M1/C120. Analog ComparatorThe Analog Comparator compares the input values on the positive pin ACMPx and negative pinACMP

2597647A–AVR–02/08ATmega32/64/M1/C1Figure 20-1. Analog Comparator Block Diagram(1)(2)Notes: 1. ADC multiplexer output: see Table 18-5 on page 243.2. R

267647A–AVR–02/08ATmega32/64/M1/C1TABLE 1. Assembly Code ExampleEEPROM_write:; Wait for completion of previous writesbic EECR,EEWErjmp EEPROM_write

2607647A–AVR–02/08ATmega32/64/M1/C120.4 Analog Comparator Register DescriptionEach analog comparator has its own control register.A dedicated register

2617647A–AVR–02/08ATmega32/64/M1/C120.4.2 Analog Comparator 1Control Register – AC1CON• Bit 7– AC1EN: Analog Comparator 1 Enable Bit Set this bit to e

2627647A–AVR–02/08ATmega32/64/M1/C1These 3 bits determine the input of the negative input of the analog comparator.The different setting are shown in

2637647A–AVR–02/08ATmega32/64/M1/C1These 3 bits determine the input of the negative input of the analog comparator.The different setting are shown in

2647647A–AVR–02/08ATmega32/64/M1/C1These 3 bits determine the input of the negative input of the analog comparator.The different setting are shown in

2657647A–AVR–02/08ATmega32/64/M1/C1AC3O bit is directly the output of the Analog comparator 2.Set when the output of the comparator is high.Cleared wh

2667647A–AVR–02/08ATmega32/64/M1/C121. Digital to Analog Converter - DAC21.1 Features• 10 bits resolution• 8 bits linearity• +/- 0.5 LSB accuracy betw

2677647A–AVR–02/08ATmega32/64/M1/C1Figure 21-1. Digital to Analog Converter Block Schematic21.2 OperationThe Digital to Analog Converter generates an

2687647A–AVR–02/08ATmega32/64/M1/C1rupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing aninterrupt. However, the in

2697647A–AVR–02/08ATmega32/64/M1/C1• Bit 2 – DALA: Digital to Analog Left Adjust Set this bit to left adjust the DAC input data.Clear it to right adju

277647A–AVR–02/08ATmega32/64/M1/C1The next code examples show assembly and C functions for reading the EEPROM. The exam-ples assume that interrupts ar

2707647A–AVR–02/08ATmega32/64/M1/C1To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediatevalue, the DAC input v

2717647A–AVR–02/08ATmega32/64/M1/C122. debugWIRE On-chip Debug System22.1 Features• Complete Program Flow Control• Emulates All On-chip Functions, Bot

2727647A–AVR–02/08ATmega32/64/M1/C1• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for

2737647A–AVR–02/08ATmega32/64/M1/C1dent Boot Loader program. The Boot Loader program can use any available data interface andassociated protocol to re

2747647A–AVR–02/08ATmega32/64/M1/C1Note that the user software can never read any code that is located inside the RWW section dur-ing a Boot Loader so

2757647A–AVR–02/08ATmega32/64/M1/C1Figure 23-1. Read-While-Write vs. No Read-While-WriteRead-While-Write(RWW) SectionNo Read-While-Write (NRWW) Sectio

2767647A–AVR–02/08ATmega32/64/M1/C1Figure 23-2. Memory SectionsNote: 1. The parameters in the figure above are given in Table 23-7 on page 286.23.4 Bo

2777647A–AVR–02/08ATmega32/64/M1/C1Note: 1. “1” means unprogrammed, “0” means programmedNote: 1. “1” means unprogrammed, “0” means programmed23.5 Ente

2787647A–AVR–02/08ATmega32/64/M1/C123.5.1 Store Program Memory Control and Status Register – SPMCSRThe Store Program Memory Control and Status Registe

2797647A–AVR–02/08ATmega32/64/M1/C1clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section isaddressed.• Bit 1 – PG

287647A–AVR–02/08ATmega32/64/M1/C14.4 I/O MemoryThe I/O space definition of the ATmega32/64/M1/C1 is shown in “Register Summary” on page346.All ATmega

2807647A–AVR–02/08ATmega32/64/M1/C1Figure 23-3. Addressing the Flash During SPM(1)Note: 1. The different variables used in Figure 23-3 are listed in T

2817647A–AVR–02/08ATmega32/64/M1/C123.7.1 Performing Page Erase by SPMTo execute Page Erase, set up the address in the Z-pointer, write “X0000011” to

2827647A–AVR–02/08ATmega32/64/M1/C123.7.7 Setting the Boot Loader Lock Bits by SPMTo set the Boot Loader Lock bits, write the desired data to R0, writ

2837647A–AVR–02/08ATmega32/64/M1/C1value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below.Refer to Table 24-4

2847647A–AVR–02/08ATmega32/64/M1/C13. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-vent the CPU from attempting

2857647A–AVR–02/08ATmega32/64/M1/C1; re-enable the RWW sectionldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)call Do_spm; read back and check, opti

2867647A–AVR–02/08ATmega32/64/M1/C123.7.14 ATmega32/64/M1/C1 - 32K -Flash Boot Loader ParametersIn Table 23-7 through Table 23-9, the parameters used

2877647A–AVR–02/08ATmega32/64/M1/C1See “Addressing the Flash During Self-Programming” on page 279 for details about the use of Z-pointer during Self-P

2887647A–AVR–02/08ATmega32/64/M1/C123.7.15 ATmega32/64/M1/C1 - 64K - Flash Boot Loader ParametersIn Table 23-7 through Table 23-9, the parameters used

2897647A–AVR–02/08ATmega32/64/M1/C1See “Addressing the Flash During Self-Programming” on page 279 for details about the use of Z-pointer during Self-P

297647A–AVR–02/08ATmega32/64/M1/C15. System Clock5.1 Clock Systems and their DistributionFigure 5-1 presents the principal clock systems in the AVR an

2907647A–AVR–02/08ATmega32/64/M1/C1Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.2. “1” means unprogrammed, “0

2917647A–AVR–02/08ATmega32/64/M1/C1Note: 1. See Table 7-2 on page 47 for BODLEVEL Fuse decoding.24.3 PSC Output Behavior During ResetFor external comp

2927647A–AVR–02/08ATmega32/64/M1/C1Note: 1. See “Alternate Functions of Port C” on page 71 for description of RSTDISBL Fuse.2. The SPIEN Fuse is not a

2937647A–AVR–02/08ATmega32/64/M1/C1the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched onPower-up in Normal mode.

2947647A–AVR–02/08ATmega32/64/M1/C1Figure 24-1. Parallel ProgrammingTable 24-8. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function

2957647A–AVR–02/08ATmega32/64/M1/C1Table 24-10. XA1 and XA0 CodingXA1 XA0 Action when XTAL1 is Pulsed00Load Flash or EEPROM Address (High or low addre

2967647A–AVR–02/08ATmega32/64/M1/C124.7 Serial Programming Pin Mapping24.8 Parallel Programming24.8.1 Enter Programming ModeThe following algorithm pu

2977647A–AVR–02/08ATmega32/64/M1/C1changed. A Chip Erase must be performed before the Flash and/or EEPROM arereprogrammed.Note: 1. The EEPRPOM memory

2987647A–AVR–02/08ATmega32/64/M1/C1eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)in the address

2997647A–AVR–02/08ATmega32/64/M1/C1Figure 24-3. Programming the Flash Waveforms(1)Note: 1. “XX” is don’t care. The letters refer to the programming de

37647A–AVR–02/08ATmega32/64/M1/C11. Pin ConfigurationsFigure 1-1. ATmega32/64M1 TQFP32/QFN32 (7*7 mm) Package.Note: On the engineering samples, the AC

307647A–AVR–02/08ATmega32/64/M1/C15.1.4 PLL Clock – clkPLLThe PLL clock allows the fast peripherals to be clocked directly from a 64/32 MHz clock. A 1

3007647A–AVR–02/08ATmega32/64/M1/C1Figure 24-4. Programming the EEPROM Waveforms24.8.6 Reading the FlashThe algorithm for reading the Flash memory is

3017647A–AVR–02/08ATmega32/64/M1/C11. A: Load Command “0100 0000”.2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.3

3027647A–AVR–02/08ATmega32/64/M1/C11. A: Load Command “0000 0100”.2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now

3037647A–AVR–02/08ATmega32/64/M1/C124.8.15 Parallel Programming CharacteristicsFigure 24-7. Parallel Programming Timing, Including some General Timing

3047647A–AVR–02/08ATmega32/64/M1/C1Figure 24-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)Note:

3057647A–AVR–02/08ATmega32/64/M1/C1Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bitscommands.2. tWLRH_

3067647A–AVR–02/08ATmega32/64/M1/C1When reading data from the ATmega32/64/M1/C1, data is clocked on the falling edge of SCK.See Figure 24-11 for timin

3077647A–AVR–02/08ATmega32/64/M1/C1a new byte, the programmed value will read correctly. This is used to determine when the nextbyte can be written. T

3087647A–AVR–02/08ATmega32/64/M1/C1Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x =

3097647A–AVR–02/08ATmega32/64/M1/C125. Electrical CharacteristicsAll DC/AC characteristics contained in this datasheet are based on simulations and ch

317647A–AVR–02/08ATmega32/64/M1/C1frequency of the Watchdog Oscillator is voltage dependent as shown in “Watchdog OscillatorFrequency vs. VCC” on page

3107647A–AVR–02/08ATmega32/64/M1/C125.2 DC CharacteristicsTA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition

3117647A–AVR–02/08ATmega32/64/M1/C1Note: 1. “Max” means the highest value where the pin is guaranteed to be read as low2. “Min” means the lowest value

3127647A–AVR–02/08ATmega32/64/M1/C125.3 Clock Characteristics25.3.1 Calibrated Internal RC Oscillator Accuracy25.4 External Clock Drive Characteristic

3137647A–AVR–02/08ATmega32/64/M1/C1Figure 25-2. Maximum Frequency vs. VCC, ATmega32/64/M1/C125.6 PLL Characteristics.Note: While connected to external

3147647A–AVR–02/08ATmega32/64/M1/C125.7 SPI Timing CharacteristicsSee Figure 25-3 and Figure 25-4 for details.Note: In SPI Programming mode the minimu

3157647A–AVR–02/08ATmega32/64/M1/C1Figure 25-4. SPI Interface Timing Requirements (Slave Mode)MISO(Data Output)SCK(CPOL = 1)MOSI(Data Input)SCK(CPOL =

3167647A–AVR–02/08ATmega32/64/M1/C125.8 ADC CharacteristicsTable 25-2. ADC Characteristics - TA = -40°C to +125°C, VCC = 2.7V to 5.5V (unless otherwis

3177647A–AVR–02/08ATmega32/64/M1/C1Zero Error (Offset)Single Ended ConversionVCC = 4.5V, VREF = 4VADC clock = 1MHz-4 0 LSBSingle Ended ConversionVCC =

3187647A–AVR–02/08ATmega32/64/M1/C125.9 Parallel Programming CharacteristicsFigure 25-5. Parallel Programming Timing, Including some General Timing Re

3197647A–AVR–02/08ATmega32/64/M1/C1Figure 25-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)Note:

327647A–AVR–02/08ATmega32/64/M1/C1Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.2. This option should not be used with

3207647A–AVR–02/08ATmega32/64/M1/C1Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bitscommands.2. tWLRH_

3217647A–AVR–02/08ATmega32/64/M1/C126.1 Active Supply CurrentFigure 26-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)Figure 26-2. Active Suppl

3227647A–AVR–02/08ATmega32/64/M1/C1Figure 26-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)Figure 26-4. Active Supply Current vs. VC

3237647A–AVR–02/08ATmega32/64/M1/C126.2 Idle Supply CurrentFigure 26-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)Figure 26-6. Idle Supply Curr

3247647A–AVR–02/08ATmega32/64/M1/C1Figure 26-7. IIdle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)Figure 26-8. Idle Supply Current vs. VCC (

3257647A–AVR–02/08ATmega32/64/M1/C1are controlled by the Power Reduction Register. See “Power Reduction Register” on page 41 fordetails.It is possible

3267647A–AVR–02/08ATmega32/64/M1/C126.3 Power-Down Supply CurrentFigure 26-9. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)Figure 26-10.

3277647A–AVR–02/08ATmega32/64/M1/C126.4 Standby Supply CurrentFigure 26-11. Standby Supply Current vs. VCC (Crystal Oscillator)26.5 Pin Pull-upFigure

3287647A–AVR–02/08ATmega32/64/M1/C1Figure 26-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V)Figure 26-14. Reset Pull-Up Resistor C

3297647A–AVR–02/08ATmega32/64/M1/C1Figure 26-15. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)26.6 Pin Driver StrengthFigure 26-16

337647A–AVR–02/08ATmega32/64/M1/C1ibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration inTable 25-1 on page 312

3307647A–AVR–02/08ATmega32/64/M1/C1Figure 26-17. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)Figure 26-18. I/O Pin Sink Current vs. Output V

3317647A–AVR–02/08ATmega32/64/M1/C1Figure 26-19. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)26.7 Pin Thresholds and HysteresisFigure 26-20. I

3327647A–AVR–02/08ATmega32/64/M1/C1Figure 26-21. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0')Figure 26-22. I/O Pin Inp

3337647A–AVR–02/08ATmega32/64/M1/C1Figure 26-23. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1')Figure 26-24. Reset Input

3347647A–AVR–02/08ATmega32/64/M1/C1Figure 26-25. Reset Input Pin Hysteresis vs. VCCFigure 26-26. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read

3357647A–AVR–02/08ATmega32/64/M1/C1Figure 26-27. XTAL1 Input Threshold Voltage vs. VCC (XTAL1 Pin Read As '0')Figure 26-28. PE0 Input Thresh

3367647A–AVR–02/08ATmega32/64/M1/C1Figure 26-29. PE0 Input Threshold Voltage vs. VCC (PE0 Pin Read As '0')26.8 BOD Thresholds and Analog Com

3377647A–AVR–02/08ATmega32/64/M1/C1Figure 26-31. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V)Figure 26-32. TypicalAnalog Comparator Hysterisis Av

3387647A–AVR–02/08ATmega32/64/M1/C126.9 Analog ReferenceFigure 26-33. AREF Voltage vs. VCCFigure 26-34. AREF Voltage vs. TemperatureAREF VOLTAGE vs. V

3397647A–AVR–02/08ATmega32/64/M1/C126.10 Internal Oscillator SpeedFigure 26-35. Watchdog Oscillator Frequency vs. VCCFigure 26-36. Calibrated 8 MHz RC

347647A–AVR–02/08ATmega32/64/M1/C1The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives thelowest frequency r

3407647A–AVR–02/08ATmega32/64/M1/C1Figure 26-37. Calibrated 8 MHz RC Oscillator Frequency vs. VCCFigure 26-38. Calibrated 8 MHz RC Oscillator Frequenc

3417647A–AVR–02/08ATmega32/64/M1/C126.11 Current Consumption of Peripheral UnitsFigure 26-39. Brownout Detector Current vs. VCCFigure 26-40. ADC Curre

3427647A–AVR–02/08ATmega32/64/M1/C1Figure 26-41. Aref Current vs. VCC (ADC at 1 MHz)Figure 26-42. Analog Comparator Current vs. VCCAREF vs. VCCADC AT

3437647A–AVR–02/08ATmega32/64/M1/C1Figure 26-43. Programming Current vs. VCC 26.12 Current Consumption in Reset and Reset Pulse widthFigure 26-44. Res

3447647A–AVR–02/08ATmega32/64/M1/C1Figure 26-45. Reset Supply Current vs. VCC (1 - 24 MHz, Excluding Current through the Reset Pull-up)Figure 26-46. R

3457647A–AVR–02/08ATmega32/64/M1/C1Figure 26-47. Reset Pulse Width vs. VCCRESET PULSE WIDTH vs. VCCEx t Cloc k 1 MHz105 °C85 °C25 °C-40 °C020040060080

3467647A–AVR–02/08ATmega32/64/M1/C127. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(0xFF) Reserved – – – – – – –

3477647A–AVR–02/08ATmega32/64/M1/C1(0xBE) Reserved – – – – – – – –(0xBD) Reserved – – – – – – – –(0xBC)(5)PIFR – – – – PEV2 PEV1 PEV0 PEOP page 155(0x

3487647A–AVR–02/08ATmega32/64/M1/C1(0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 241(0x7B) ADCSRB ADHSM ISRCEN AREFEN – ADTS3 ADTS2 ADTS1

3497647A–AVR–02/08ATmega32/64/M1/C1Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O m

357647A–AVR–02/08ATmega32/64/M1/C1Figure 5-3. PCK Clocking System5.6.2 PLL Control and Status Register – PLLCSR• Bit 7..3 – Res: Reserved BitsThese bi

3507647A–AVR–02/08ATmega32/64/M1/C128. Instruction Set SummaryMnemonics Operands Description Operation Flags #ClocksARITHMETIC AND LOGIC INSTRUCTIONSA

3517647A–AVR–02/08ATmega32/64/M1/C1BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2BRID k Branch if Interrupt Disabled i

3527647A–AVR–02/08ATmega32/64/M1/C1Note: 1. These Instructions are only available in “16K and 32K parts”POP Rd Pop Register from Stack Rd ← STACK None

3537647A–AVR–02/08ATmega32/64/M1/C129. Errata 29.1 Errata Summary29.1.1 ATmega32/64/M1/C1 Rev. A (Mask Revision)• Inopportune reset of the CANIDM regi

3547647A–AVR–02/08ATmega32/64/M1/C130. Ordering InformationFigure 30-1. ATmega32M1 engineering samples delivery only. Automotive qualification not yet

3557647A–AVR–02/08ATmega32/64/M1/C131. Package InformationPackage TypeMAMA, 32 - Lead, 7x7 mm Body Size, 1.0 mm Body Thickness0.5 mm Lead Pitch, Thin

3567647A–AVR–02/08ATmega32/64/M1/C131.1 TQFP32

3577647A–AVR–02/08ATmega32/64/M1/C131.2 QFN32

3587647A–AVR–02/08ATmega32/64/M1/C132. Datasheet Revision History for ATmega32/64/M1/C1Please note that the referring page numbers in this section are

3597647A–AVR–02/08ATmega32/64/M1/C1Features... 11 Pi

367647A–AVR–02/08ATmega32/64/M1/C1Figure 5-4. External Clock Drive ConfigurationWhen this clock source is selected, start-up times are determined by t

3607647A–AVR–02/08ATmega32/64/M1/C16 Power Management and Sleep Modes ... 396.1 Sleep Mode Control Regis

3617647A–AVR–02/08ATmega32/64/M1/C112.7 Timer/Counter Timing Diagrams ...9812.8 8-b

3627647A–AVR–02/08ATmega32/64/M1/C116 Controller Area Network - CAN ... 16716.1 Features ...

3637647A–AVR–02/08ATmega32/64/M1/C119.3 Control Register ...

3647647A–AVR–02/08ATmega32/64/M1/C124.8 Parallel Programming ...29624

3657647A–AVR–02/08ATmega32/64/M1/C132 Datasheet Revision History for ATmega32/64M1 ... 35832.1 7647A ...

7647A–AVR–02/08Headquarters InternationalAtmel Corporation2325 Orchard ParkwaySan Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel AsiaR

377647A–AVR–02/08ATmega32/64/M1/C1When switching between prescaler settings, the System Clock Prescaler ensures that noglitches occurs in the clock sy

387647A–AVR–02/08ATmega32/64/M1/C1the selcted clock source has a higher frequency than the maximum frequency of the device atthe present operating con

397647A–AVR–02/08ATmega32/64/M1/C16. Power Management and Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, thereb

47647A–AVR–02/08ATmega32/64/M1/C1Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (7*7 mm) PackageNote: On the engineering samples, the ACMPN3 alternate functio

407647A–AVR–02/08ATmega32/64/M1/C16.2 Idle ModeWhen the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idlemode, stopping t

417647A–AVR–02/08ATmega32/64/M1/C1with the exception that the Oscillator is kept running. From Standby mode, the device wakes upin six clock cycles. N

427647A–AVR–02/08ATmega32/64/M1/C1Writing a logic one to this bit reduces the consumption of the PSC by stopping the clock to thismodule. When waking

437647A–AVR–02/08ATmega32/64/M1/C1nificantly to the total current consumption. Refer to “Brown-out Detection” on page 47 for detailson how to configur

447647A–AVR–02/08ATmega32/64/M1/C17. System Control and Reset7.1 Resetting the AVRDuring reset, all I/O Registers are set to their initial values, and

457647A–AVR–02/08ATmega32/64/M1/C1Figure 7-1. Reset LogicNote: 1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a Reset.7.

467647A–AVR–02/08ATmega32/64/M1/C1Figure 7-2. MCU Start-up, RESET Tied to VCCFigure 7-3. MCU Start-up, RESET Extended Externally7.2.2 External ResetAn

477647A–AVR–02/08ATmega32/64/M1/C17.2.3 Brown-out DetectionATmega32/64/M1/C1 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCCle

487647A–AVR–02/08ATmega32/64/M1/C1Figure 7-5. Brown-out Reset During Operation7.2.4 Watchdog ResetWhen the Watchdog times out, it will generate a shor

497647A–AVR–02/08ATmega32/64/M1/C1This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing alogic zero to the

57647A–AVR–02/08ATmega32/64/M1/C11.1 Pin Descriptions: Table 1-1. Pin out description QFN32 Pin Number Mnemonic Type Name, Function & Alternate Fu

507647A–AVR–02/08ATmega32/64/M1/C17.4 Watchdog TimerATmega32/64/M1/C1 has an Enhanced Watchdog Timer (WDT). The main features are:•Clocked from separa

517647A–AVR–02/08ATmega32/64/M1/C1The following code example shows one assembly and one C function for turning off the Watch-dog Timer. The example as

527647A–AVR–02/08ATmega32/64/M1/C1The following code example shows one assembly and one C function for changing the time-outvalue of the Watchdog Time

537647A–AVR–02/08ATmega32/64/M1/C1• Bit 6 - WDIE: Watchdog Interrupt EnableWhen this bit is written to one and the I-bit in the Status Register is set

547647A–AVR–02/08ATmega32/64/M1/C1.Table 7-6. Watchdog Timer Prescale SelectWDP3 WDP2 WDP1 WDP0Number of WDT Oscillator CyclesTypical Time-out at VCC

557647A–AVR–02/08ATmega32/64/M1/C18. InterruptsThis section describes the specifics of the interrupt handling as performed inATmega32/64/M1/C1. For a

567647A–AVR–02/08ATmega32/64/M1/C1Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address atreset, see “Boot Lo

577647A–AVR–02/08ATmega32/64/M1/C10x020 jmp TIM0_COMPB ; Timer0 Compare B Handler0x022 jmp TIM0_OVF ; Timer0 Overflow Handler0x024 jmp CAN_INT ; CAN M

587647A–AVR–02/08ATmega32/64/M1/C10x03C jmp SPM_RDY ; Store Program Memory Ready Handler;.org 0xC000xC00 RESET: ldi r16,high(RAMEND); Main program

597647A–AVR–02/08ATmega32/64/M1/C11. Write the Interrupt Vector Change Enable (IVCE) bit to one.2. Within four cycles, write the desired value to IVSE

67647A–AVR–02/08ATmega32/64/M1/C13 PC1 I/OPSCIN1 (PSC Digital Input 1) OC1B (Timer 1 Output Compare B)SS_A (Alternate SPI Slave Select)PCINT9 (Pin Cha

607647A–AVR–02/08ATmega32/64/M1/C19. I/O-Ports9.1 IntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digital I/O

617647A–AVR–02/08ATmega32/64/M1/C19.2 Ports as General Digital I/OThe ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 s

627647A–AVR–02/08ATmega32/64/M1/C1If PORTxn is written logic one when the pin is configured as an output pin, the port pin is drivenhigh (one). If POR

637647A–AVR–02/08ATmega32/64/M1/C1Figure 9-3. Synchronization when Reading an Externally Applied Pin valueConsider the clock period starting shortly a

647647A–AVR–02/08ATmega32/64/M1/C1values are read back again, but as previously discussed, a nop instruction is included to be ableto read back the va

657647A–AVR–02/08ATmega32/64/M1/C19.3 Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os. Figur

667647A–AVR–02/08ATmega32/64/M1/C1The following subsections shortly describe the alternate functions for each port, and relate theoverriding signals t

677647A–AVR–02/08ATmega32/64/M1/C19.3.1 MCU Control Register – MCUCR• Bit 4 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the

687647A–AVR–02/08ATmega32/64/M1/C1ADC4, Analog to Digital Converter, input channel 4.SCK, Master Clock output, Slave Clock input pin for SPI channel.

697647A–AVR–02/08ATmega32/64/M1/C1MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as amaster, this pin is conf

77647A–AVR–02/08ATmega32/64/M1/C1Note: 1. Only for ATmega32/64M1.2. On the engineering samples, the ACMPN3 alternate function is not located on PC4. I

707647A–AVR–02/08ATmega32/64/M1/C1Table 9-5. Overriding Signals for Alternate Functions in PB3..PB0Signal NamePB3/AMP0-/PCINT3PB2/ADC5/INT1/ACMPN0/PCI

717647A–AVR–02/08ATmega32/64/M1/C19.3.3 Alternate Functions of Port CThe Port C pins with alternate functions are shown in Table 9-6.Note: On the engi

727647A–AVR–02/08ATmega32/64/M1/C1ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as input with the internalpull-up switched off to

737647A–AVR–02/08ATmega32/64/M1/C1PSCOUT1A, Output 1A of PSC.INT3, External Interrupt source 3: This pin can serve as an external interrupt source to

747647A–AVR–02/08ATmega32/64/M1/C19.3.4 Alternate Functions of Port DThe Port D pins with alternate functions are shown in Table 9-9.The alternate pin

757647A–AVR–02/08ATmega32/64/M1/C1ACMPN2, Analog Comparator 2 Negative Input. Configure the port pin as input with the internalpull-up switched off to

767647A–AVR–02/08ATmega32/64/M1/C1MISO_A: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled asa master, this pin is co

777647A–AVR–02/08ATmega32/64/M1/C1 9.3.5 Alternate Functions of Port EThe Port E pins with alternate functions are shown in Table 9-12.Note: On the en

787647A–AVR–02/08ATmega32/64/M1/C1The alternate pin configuration is as follows:• PCINT26/XTAL2/ADC0 – Bit 2XTAL2: Chip clock Oscillator pin 2. Used a

797647A–AVR–02/08ATmega32/64/M1/C19.4 Register Description for I/O-Ports9.4.1 Port B Data Register – PORTB9.4.2 Port B Data Direction Register – DDRB9

87647A–AVR–02/08ATmega32/64/M1/C12.1 Block DiagramFigure 2-1. Block DiagramThe AVR core combines a rich instruction set with 32 general purpose workin

807647A–AVR–02/08ATmega32/64/M1/C19.4.9 Port D Input Pins Address – PIND9.4.10 Port E Data Register – PORTE9.4.11 Port E Data Direction Register – DDR

817647A–AVR–02/08ATmega32/64/M1/C110. External InterruptsThe External Interrupts are triggered by the INT3:0 pins or any of the PCINT23..0 pins. Obser

827647A–AVR–02/08ATmega32/64/M1/C110.2 External Interrupt Control Register A – EICRAThe External Interrupt Control Register A contains control bits fo

837647A–AVR–02/08ATmega32/64/M1/C110.2.2 External Interrupt Flag Register – EIFR• Bit 7..4 – Res: Reserved BitsThese bits are unused bits in the ATmeg

847647A–AVR–02/08ATmega32/64/M1/C110.2.4 Pin Change Interrupt Flag Register - PCIFR• Bit 7..4 - Res: Reserved BitsThese bits are unused bits in the AT

857647A–AVR–02/08ATmega32/64/M1/C110.2.6 Pin Change Mask Register 2 – PCMSK2• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16Each PCINT23..16-bi

867647A–AVR–02/08ATmega32/64/M1/C111. Timer/Counter0 and Timer/Counter1 PrescalersTimer/Counter1 and Timer/Counter0 share the same prescaler module, b

877647A–AVR–02/08ATmega32/64/M1/C1Each half period of the external clock applied must be longer than one system clock cycle toensure correct sampling.

887647A–AVR–02/08ATmega32/64/M1/C1Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PC3). The selectionis made thanks to ICPSEL1

897647A–AVR–02/08ATmega32/64/M1/C112. 8-bit Timer/Counter0 with PWMTimer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independen

97647A–AVR–02/08ATmega32/64/M1/C1The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN,LIN/UART and interrupt system to

907647A–AVR–02/08ATmega32/64/M1/C1The definitions in Table 12-1 are also used extensively throughout the document.12.1.2 RegistersThe Timer/Counter (T

917647A–AVR–02/08ATmega32/64/M1/C1count Increment or decrement TCNT0 by 1.direction Select between increment and decrement.clear Clear TCNT0 (set all

927647A–AVR–02/08ATmega32/64/M1/C1Figure 12-3. Output Compare Unit, Block DiagramThe OCR0x Registers are double buffered when using any of the Pulse W

937647A–AVR–02/08ATmega32/64/M1/C1The setup of the OC0x should be performed before setting the Data Direction Register for theport pin to output. The

947647A–AVR–02/08ATmega32/64/M1/C1non-PWM modes refer to Table 12-2 on page 100. For fast PWM mode, refer to Table 12-3 onpage 100, and for phase corr

957647A–AVR–02/08ATmega32/64/M1/C1Figure 12-5. CTC Mode, Timing DiagramAn interrupt can be generated each time the counter value reaches the TOP value

967647A–AVR–02/08ATmega32/64/M1/C1inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent comparematches between OCR0x and

977647A–AVR–02/08ATmega32/64/M1/C112.6.4 Phase Correct PWM ModeThe phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correctP

987647A–AVR–02/08ATmega32/64/M1/C1match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for theoutput when using phase correct

997647A–AVR–02/08ATmega32/64/M1/C1Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)Figure 12-10 shows the setting of OCF0B in all