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_______________General Description
The MAX194 is a 14-bit successive-approximation ana-
log-to-digital converter (ADC) that combines high
speed, high accuracy, low power consumption, and a
10µA shutdown mode. Internal calibration circuitry cor-
rects linearity and offset errors to maintain the full rated
performance over the operating temperature range
without external adjustments. The capacitive-DAC
architecture provides an inherent 85ksps track/hold
function.
The MAX194, with an external reference (up to +5V),
offers a unipolar (0V to V
REF
) or bipolar (-V
REF
to V
REF
)
pin-selectable input range. Separate analog and digital
supplies minimize digital-noise coupling.
The chip select (CS) input controls the three-state seri-
al-data output. The output can be read either during
conversion as the bits are determined, or following con-
version at up to 5Mbps using the serial clock (SCLK).
The end-of-conversion (EOC) output can be used to
interrupt a processor, or can be connected directly to
the convert input (CONV) for continuous, full-speed
conversions.
The MAX194 is available in 16-pin DIP, wide SO, and
ceramic sidebraze packages. The output data format
provides pin-for-pin and functional compatibility with
the 16-bit MAX195 ADC.
________________________Applications
Portable Instruments Audio
Industrial Controls Robotics
Multiple Transducer Medical Signal
Measurements Acquisition
Vibrations Analysis Digital Signal
Processing
____________________________Features
True 14-Bit Accuracy:
1
2
LSB INL
82dB SINAD
9.4µs Conversion Time
10µA Shutdown Mode
Built-In Track/Hold
AC and DC Specified
Unipolar (0V to V
REF
) and Bipolar (-V
REF
to V
REF
)
Input Range
Three-State Serial-Data Output
Small 16-Pin DIP, SO, and Ceramic SB Packages
Pin-Compatible 16-Bit Upgrade (MAX195)
______________Ordering Information
MAX194
14-Bit, 85ksps ADC with 10µA Shutdown
________________________________________________________________
Maxim Integrated Products
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDDA
VSSA
AGND
AIN
VDDD
SCLK
CLK
BP/UP/SHDN
TOP VIEW
MAX194
REF
VSSD
RESET
CONV
CS
EOC
DGND
DOUT
DIP/Wide SO/Ceramic SB
MAX194
AIN
REF
CONV
SCLK
CLK
BP/UP/SHDN
CS
RESET
VSSD
DGND
VDDD
VDDA
AGND
VSSA
DOUT
EOC
SAR
CONTROL LOGIC
COMPARATOR
CALIBRATION
DACs
THREE-STATE BUFFER
4
6
11
16
14
15
5
7
10
8
1
9
3
2
13
12
MAIN DAC
Σ
________________Functional Diagram
__________________Pin Configuration
19-0345; Rev 4; 12/97
PART
MAX194ACPE
MAX194BCPE
MAX194ACWE 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 Wide SO
MAX194BCWE 0°C to +70°C 16 Wide SO
MAX194AEPE -40°C to +85°C 16 Plastic DIP
MAX194BEPE -40°C to +85°C 16 Plastic DIP
MAX194AEWE -40°C to +85°C 16 Wide SO
MAX194BEWE -40°C to +85°C 16 Wide SO
MAX194AMDE -55°C to +125°C 16 Ceramic SB
MAX194BMDE -55°C to +125°C 16 Ceramic SB
EVALUATION KIT
AVAILABLE
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
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Inhaltsverzeichnis

Seite 1 - Maxim Integrated Products

_______________General DescriptionThe MAX194 is a 14-bit successive-approximation ana-log-to-digital converter (ADC) that combines highspeed, high acc

Seite 2 - ELECTRICAL CHARACTERISTICS

MAX194mum (1.7MHz), reading the data after each conversion(during the acquisition time) results in lower throughput(about 70ksps max) than reading the

Seite 3

MAX19414-Bit, 85ksps ADC with 10µA Shutdown______________________________________________________________________________________ 11BRIDGEINSTRUMENTAT

Seite 4 - TIMING CHARACTERISTICS

MAX194be improved by trimming, but the drift is too great toprovide good stability over temperature. The MAX427buffer provides the necessary drive cur

Seite 5

MAX19414-Bit, 85ksps ADC with 10µA Shutdown______________________________________________________________________________________ 13INPUTSIGNAL1N914DI

Seite 6 - Calibration

MAX194REF and AIN Input ProtectionThe REF and AIN signals should not exceed theMAX194 supply rails. If this can occur, diode clamp thesignal to the su

Seite 7 - Digital Interface

Input Acquisition and SettlingFour conversion-clock periods are allocated for acquir-ing the input signal. At the highest conversion rate, fourclock p

Seite 8 - Output Data

MAX194DC AccuracyIf DC accuracy is important, choose a buffer with anoffset much less than the MAX194’s maximum offset(±1 LSB = ±488µV for a ±4V input

Seite 9 - Modes and SPI/QSPI Interfaces

Data is clocked out of the MAX194 on CLK’s fallingedge and can be clocked into the µP on the risingedge or the following falling edge. If you clock da

Seite 10

MAX194Complete source code for the Motorola 68HC16 andthe MAX194 evaluation kit (EV kit) using this mode isavailable in the MAX194 EV kit manual.Mode

Seite 11 - Reference

MAX19414-Bit, 85ksps ADC with 10µA Shutdown______________________________________________________________________________________ 19Figure 21. MAX194

Seite 12

MAX19414-Bit, 85ksps ADC with 10µA Shutdown2 _______________________________________________________________________________________ABSOLUTE MAXIMUM R

Seite 13

MAX19414-Bit, 85ksps ADC with 10µA Shutdown20 ______________________________________________________________________________________Figure 21. MAX194

Seite 14 - Analog Input

MAX19414-Bit, 85ksps ADC with 10µA Shutdown______________________________________________________________________________________ 21Constraints on seq

Seite 15 - Distortion

MAX19414-Bit, 85ksps ADC with 10µA Shutdown22 ______________________________________________________________________________________MAX19410µFVDDDVDDA

Seite 16 - Mode 1 (Simultaneous

MAX19414-Bit, 85ksps ADC with 10µA Shutdown______________________________________________________________________________________ 23measure of the ADC

Seite 17 - Electrical Characteristics

MAX19414-Bit, 85ksps ADC with 10µA ShutdownSpurious-Free Dynamic RangeSpurious-free dynamic range is the ratio of the funda-mental RMS amplitude to th

Seite 18 - Supplies, Layout, Grounding

MAX19414-Bit, 85ksps ADC with 10µA Shutdown_______________________________________________________________________________________ 3ELECTRICAL CHARACT

Seite 19

MAX19414-Bit, 85ksps ADC with 10µA Shutdown4 _______________________________________________________________________________________VDDD = VDDA = 5.25

Seite 20

_______________Detailed DescriptionThe MAX194 uses a successive-approximation register(SAR) to convert an analog input to a 14-bit digitalcode, which

Seite 21 - Shutdown

MAX194CalibrationIn an ideal DAC, each of the capacitors associated withthe data bits would be exactly twice the value of thenext smaller capacitor. I

Seite 22 - Effective Number of Bits

If the power supplies do not settle within the MAX194’spower-on delay (500ns minimum), power-up calibrationmay begin with supply voltages that differ

Seite 23 - Total Harmonic Distortion

MAX194sion and EOC will go high on the following CLK fallingedge (Figure 4). CONV is ignored during conversions.External ClockThe conversion clock (CL

Seite 24 - Transfer Function

If you read the data bits between conversions, you can 1) count CLK cycles until the end of the conversion, or 2) poll EOC to determine when the conve

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