
2
9117C–AUTO–10/09
ATA6628/ATA6630 [Preliminary]
Figure 1-1. Block Diagram
High
Speed
Mode
Adjustable
Watchdog
Oscillator
Short Circuit and
Overtemperature
Protection
TXD
Time-out
Timer
Edge
Detection
Debounce
Time
Internal Testing
Unit
Control Unit
Slew Rate Control
Wake-up
Bus Timer
Mode Select
Undervoltage
Reset
Normal/Silent/
Fail-safe Mode
3.3V/50 mA/
±2%
5V/50 mA/
±2%
RF Filter
Watchdog
15
10
2
12
RXD
NTRIGGNDPV
PVCC
PVCC
PVCC
TMMODE
EN
TXD
SP_MODE
KL_15
17
WAKE
Receiver
7
4
59163
Normal and
Fail-safe
Mode
18
19
13
14
6
20
LIN
WD_OSC
NRES
PVCC
VCC
VS
8
DIV_ON
1
VBATT
5k
Normal and
Fail-safe
Mode
INH
11
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