
3
9117C–AUTO–10/09
ATA6628/ATA6630 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning QFN20
67 8 109
20 19 18
QFN 5 mm 5 mm
0.65 mm pitch
20 lead
ATA6628/3 0
16
11
12
13
14
15
INH
TXD
NRES
WD_OSC
TM
MODE
KL15
PVCC
VCC
VS
SP_MODE
PV
DIV_ON
RXD
LIN
GND
WAKE
NTRIG
EN
VBATT
5
4
3
2
1
17
Table 2-1. Pin Description
Pin Symbol Function
1 VBATT Battery supply for the voltage divider
2 EN Enables the device into Normal Mode
3 NTRIG Low-level watchdog trigger input from microcontroller; if not needed, connect to PVCC
4 WAKE High-voltage input for local wake-up request; if not needed, connect to VS
5 GND System ground
6 LIN LIN-bus line input/output
7 RXD Receive data output
8 DIV_ON Input to switch on the internal voltage divider, active high
9 PV Voltage divider output
10 SP_MODE Input to switch the transceiver in High-speed Mode, active high
11 INH Battery related High-side switch
12 TXD Transmit data input; active low output (strong pull down) after a local wake up request
13 NRES Output undervoltage and watchdog reset (open drain)
14 WD_OSC External resistor for adjustable watchdog timing; if not needed, connect to GND
15 TM For factory testing only (tie to ground)
16 MODE For Debug Mode: Low watchdog is on; high watchdog is off
17 KL_15 Ignition detection (edge sensitive)
18 PVCC 3.3V/5V regulator sense input pin, connect to VCC
19 VCC 3.3V/5V regulator output/driver pin, connect to PVCC
20 VS Battery supply
Backside Heat slug is connected to GND
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