76
ATmega169V/L
2514A–AVR–08/02
External Interrupt Mask
Register – EIMSK
• Bit 7 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the
PCMSK1 Register.
• Bit 6 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0
Register.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the External Interrupt Control Register A (EICRA) define whether the external
interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The
corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-
rupt Vector.
External Interrupt Flag
Register – EIFR
• Bit 7 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1
becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
• Bit 6 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0
becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it.
Bit 76543210
PCIE1 PCIE0
– – – – – INT0 EIMSK
Read/Write R/W R/W R R R R R R/W
InitialValue00000000
Bit 76543210
PCIF1 PCIF0
– – – – – INTF0 EIFR
Read/Write R/W R/W R R R R R R/W
InitialValue00000000
(27 Seiten)
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