
W90P710CD/W90P710CDG
- 308 -
LRCLK
BCK
DATA
Left Right
123
MSB
B2
12
LSB M SB
I2S bus
LRCLK
BCK
DATA
Left Right
123
B2
B3
12
MSB B2
M S B –Ju stified form at
MSB
LSB
Figure 6.11.2.2 The format of IIS
The sampling rate, bit shift clock frequency could be set by the control register ACTL_IISCON.
6.11.2 AC97 Interface
The AC97 interface, called AC-link is supported. For input and output direction, each frame contains a
Tag slot and 12 data slots. However, in the 12 data slots, only 4 slots are used in W90P710, other 8
slots are not supported, and the control data and audio data are transferred in the 4 valid slots. Each
slot contains 20 bits data.
The interface signals are shown as Figure 6.11.2.1
Figure 6.11.2.1 The interface signal of AC-link
Audio
Controller
Audio
Codec
SYNC
BCLK
DIN
DOUT
RESETB
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