
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 83 - Revision B2
A[21:0]
D[31:0]
nWBE_SDQM[1]
nECSn
nWE
A[21:0]
DQ[15:0]
nOE
nCS
nWE
nOE
nUB
nLB
nWBE_SDQM[0]
W90P710
2Mx16 SRAM
Fig. 6.3.8 External IO bank with 16-bit SRAM
Clock Skew Control Register (CKSKEW)
Register Address R/W Description Reset Value
CKSKEW
0xFFF0_1F00
R/W Clock skew control register 0xXXXX_0018
31 30 29 28 27 26 25 24
DLH_CLK_REF
23 22 21 20 19 18 17 16
DLH_CLK_REF
15 14 13 12 11 10 9 8
RESVERED SWPON
7 6 5 4 3 2 1 0
DLH_CLK_SKEW MCLK_O_D
Kommentare zu diesen Handbüchern