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2588B–AVR–11/06

ATtiny261/461/861

19.10.3 ADCL and ADCH – The ADC Data Register

19.10.3.1 ADLAR = 0

19.10.3.2 ADLAR = 1

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on

page 152.

19.10.4 ADCSRB – ADC Control and Status Register B

100 16

101 32

110 64

1 1 1 128

Table 19-5. ADC Prescaler Selections (Continued)

ADPS2 ADPS1 ADPS0 Division Factor

Bit 151413121110 9 8

0x05 (0x25) ––––––ADC9 ADC8 ADCH

0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/Write RRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 151413121110 9 8

0x05 (0x25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

0x04 (0x24) ADC1 ADC0 ––––––ADCL

76543210

Read/Write RRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 7 6543210

0x03 (0x23) BIN GSEL - REFS2 MUX5 ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R/W R/W R/W R R R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

1 2 ... 153 154 155 156 157 158 159 160 161 162 163 ... 235 236

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