Rainbow-electronics ATmega128RFA1 Bedienungsanleitung PDF herunterladen (Seite 324)

324

8266A-MCU Wireless-12/09

ATmega128RFA1

• Bit 1 – OCIE2A - Timer/Counter2 Output Compare Match A Interrupt Enable

When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one),

the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt

is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is

set in the Timer/Counter2 Interrupt Flag Register TIFR2.

• Bit 0 – TOIE2 - Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed

if an overflow in Timer/Counter2 occurs i.e., when the TOV2 bit is set in the

Timer/Counter2 Interrupt Flag Register TIFR2.

21.11.2 TIFR2 – Timer/Counter Interrupt Flag Register

Bit 7 6 5 4 3 2 1 0

$17 ($37) Res4 Res3 Res2 Res1 Res0 OCF2B OCF2A TOV2 TIFR2

Read/Write R R R R R RW RW RW

Initial Value 0 0 0 0 0 0 0 0

• Bit 7:3 – Res4:0 - Reserved Bit

This bit is reserved for future use. A read access always will return zero. A write access

does not modify the content.

• Bit 2 – OCF2B - Output Compare Flag 2 B

The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2

and the data in OCR2B Output Compare Register2. OCF2B is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF2B is

cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B

(Timer/Counter2 Compare Match Interrupt Enable), and OCF2B are set (one), the

Timer/Counter2 Compare Match Interrupt is executed.

• Bit 1 – OCF2A - Output Compare Flag 2 A

The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2

and the data in OCR2A Output Compare Register2. OCF2A is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF2A is

cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A

(Timer/Counter2 Compare Match Interrupt Enable), and OCF2A are set (one), the

Timer/Counter2 Compare Match Interrupt is executed.

• Bit 0 – TOV2 - Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A

(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 changes counting direction at 0x00.

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Rainbow-electronics ATmega128RFA1 Bedienungsanleitung Seite 324