100
ATmega8515(L)
2512A–AVR–04/02
Timer/Counter Clock
Sources
TheTimer/Countercan be clockedbyan internal or an externalclock source. The clock
sourceisselectedbythe Clock Select logicwhich iscontrolledbythe
Clock Select
(CS12:0)bitslocated in the
Timer/Counter Control Register B
(TCCR1B). Fordetails on
clock sources andprescaler, see “Timer/Counter0and Timer/Counter1Prescalers”on
page 92.
Counter Unit Themainpartof the16-bit Timer/Counter is the programmable16-bit bi-directional
counter unit. Figure47shows a block diagram of the counter and itssurroundings.
Figure 47. CounterUnit Block Diagram
Signaldescription (internalsignals):
Count Increment ordecrement TCNT1 by 1.
Direction Select between increment anddecrement.
Clear Clear TCNT1 (set all bits to zero).
clk
T
1
Timer/Counterclock.
TOP Signalizethat TCNT1 hasreached maximum value.
BOTTOM Signalizethat TCNT1 hasreached minimum value (zero).
The16-bit counter is mapped into two8-bit I/O memory locations:
Counter High
(TCNT1H) containing theupper eight bits of the counter, and
Counter Low
(TCNT1L)
containing the lower eight bits.TheTCNT1H Registercan only beindirectly accessed
by the CPU. When the CPUdoes an access to theTCNT1HI/Olocation, the CPU
accesses the highbyte temporary register(TEMP).Thetemporary register is updated
with theTCNT1H value when theTCNT1L isread, and TCNT1H is updatedwith the
temporary register value when TCNT1L iswritten. This allows the CPU to read orwrite
the entire16-bit counter value within one clock cycleviathe8-bit data bus. Itis impor-
tant to noticethat thereare specialcases ofwriting to theTCNT1 Registerwhen the
counter iscounting that will give unpredictable results.The specialcases are described
in the sectionswherethey areof importance.
Dependingonthemodeof operation used, the counter iscleared, incremented, ordec-
remented at each
Timer Clock
(clk
T
1
).The clk
T
1
can begeneratedfrom an external or
internalclock source,selectedbythe
Clock Select
bits(CS12:0). When no clock source
isselected(CS12:0 = 0) thetimer isstopped. However, theTCNT1 value can be
accessedbythe CPU, independent ofwhetherclk
T
1
ispresent or not. A CPUwrite over-
rides(haspriority over) all counterclear orcount operations.
The counting sequenceisdeterminedbythe setting of the
Waveform Generation mode
bits(WGM13:0)located in the
Timer/Counter Control Registers
AandB(TCCR1A and
TCCR1B).Thereare close connectionsbetween how the counterbehaves(counts) and
TEMP (8-bit)
DATA BUS
(8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn
Edge
Detector
( From Prescaler )
clk
Tn
(24 Seiten)
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