127
ATmega8515(L)
2512A–AVR–04/02
SS Pin Functionality
Slave Mode When the SPI isconfigured as a Slave, the Slave Select (SS)pin is always input. When
SS
isheld low, the SPI is activated, andMISObecomes an output ifconfiguredso by
theuser.All otherpins areinputs. When SS
isdriven high, all pins areinputs, and the
SPI ispassive,which means that it will not receive incoming data. Note that the SPI
logicwill be reset oncethe SS
pin isdriven high.
The SS
pin is usefulforpacket/byte synchronization to keep the slave bit countersyn-
chronouswith themasterclock generator. When the SS
pin isdriven high, the SPISlave
will immediately reset the send andreceive logic, anddrop anypartially receiveddata in
the shIft Register.
Master Mode When the SPI isconfigured as a Master(MSTR in SPCRisset), theusercan determine
the direction of the SS
pin.
If SS
isconfigured as an output, the pin is ageneral output pin which does not affectthe
SPI system. Typically, the pin will be driving the SS
pin of the SPISlave.
If SS
isconfigured as an input, it must be held high to ensure MasterSPI operation. If
the SS
pin isdriven lowbyperipheralcircuitry when the SPI isconfigured as a Master
with the SS
pin defined as an input, the SPIsystem interprets this as anotherMaster
selecting the SPI as a Slave andstarting to senddata to it. To avoidbuscontention, the
SPI system takes the following actions:
1. The MSTR bit in SPCRiscleared and the SPI system becomes a Slave. As a
resultof the SPIbecoming a Slave, the MOSI andSCKpinsbecome inputs.
2. The SPIF flag in SPSRisset, and if the SPI interruptis enabled, and the I-bit in
SREG isset, theinterrupt routine will beexecuted.
Thus, when interrupt-driven SPI transmission is used in Master mode, and thereexists a
possibility that SS
isdriven low, theinterrupt should always check that the MSTR bit is
still set. If the MSTR bit hasbeen clearedbya slave select, it must be set by theuser to
re-enable SPIMaster mode.
SPI Control Register – SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
Thisbit causes the SPI interrupttobeexecuted ifSPIF bit in the SPSR register isset
and theif the GlobalInterrupt Enable bit in SREG isset.
• Bit 6 – SPE: SPI Enable
When the SPEbit iswritten to one, the SPI is enabled.Thisbit must be set to enable
anySPI operations.
• Bit 5 – DORD: Data Order
When the DORDbit iswrittentoone, the LSB of the data word is transmittedfirst.
When the DORDbit iswritten to zero, the MSB of the data word is transmittedfirst.
Bit 76543 210
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
(24 Seiten)
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