Rainbow-electronics ATmega8515L Bedienungsanleitung PDF herunterladen (Seite 161)

161

ATmega8515(L)

2512A–AVR–04/02

theACIE bit isset and the I-bit in SREG isset. ACI isclearedbyhardware when execut-

ing the corresponding interrupt handling vector.Alternatively, ACI isclearedbywriting a

logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When theACIE bit iswritten logic one and the I-bit in the Status Register isset, theAna-

log Comparator interruptis activated. When written logiczero, theinterruptisdisabled.

• Bit 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, thisbit enables the Input Capture function in Timer/Counter1to

betriggeredbytheAnalog Comparator.The comparator output is in thiscase directly

connected to the Input Capture front-endlogic, making the comparator utilizethenoise

canceler and edge select features of theTimer/Counter1 Input Captureinterrupt. When

written logiczero, no connection between theAnalog Comparator and the Input Capture

function exists.Tomakethe comparator trigger theTimer/Counter1 Input Captureinter-

rupt, theTICIE1 bit in theTimerInterrupt Mask Register(TIMSK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bitsdetermine which comparator events that trigger theAnalog Comparator inter-

rupt. The different settings are showninTable 72.

When changing theACIS1/ACIS0 bits, theAnalog Comparator interruptmust be dis-

abledbyclearing itsInterrupt Enable bit in theACSR Register. Otherwiseaninterrupt

can occurwhen the bits are changed.

Table 72. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

00ComparatorInterruptonOutput Toggle

01Reserved

10ComparatorInterruptonFalling Output Edge

11ComparatorInterruptonRising Output Edge

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Rainbow-electronics ATmega8515L Bedienungsanleitung Seite 161