74
ATmega8515(L)
2512A–AVR–04/02
External Interrupts The ExternalInterrupts aretriggeredbythe INT0,INT1, andINT2 pins. Observe that, if
enabled, theinterruptswill trigger even if the INT0..2 pins are configured as outputs.
Thisfeature provides a way of generating a softwareinterrupt. The ExternalInterrupts
can betriggeredbya falling orrising edge or a lowlevel(INT2 is only an edge triggered
interrupt).This isset up as indicated in the specification for the MCU Control Register –
MCUCRandExtendedMCUControl Register – EMCUCR. When the ExternalInterrupt
is enabled and isconfigured aslevel triggered(only INT0/INT1), theinterrupt will trigger
aslong as the pin isheld low. Note that recognition offalling orrising edge interrupts on
INT0 andINT1 requires the presenceof an I/Oclock, described in “Clock Systems and
theirDistribution” on page 31. Lowlevel interrupts on INT0/INT1 and theedge interrupt
on INT2 are detected asynchronously.This implies that theseinterruptscan beusedfor
waking the partalso from sleep modes other than Idlemode. The I/Oclock ishalted in
all sleep modes except Idlemode.
Note that if a level triggered interruptis usedforwake-upfrom Power-downmode, the
changedlevel must be held forsometimetowakeup the MCU.This makes the MCU
less sensitive to noise. The changedlevel issampled twice by the Watchdog Oscillator
clock.The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C.The
frequency of the Watchdog Oscillator is voltage dependent asshownin“ElectricalChar-
acteristics”onpage 194. The MCU will wakeup if theinput has the requiredlevelduring
thissampling or if it isheld until theend of the start-up time. The start-up time isdefined
by the SUT Fuses asdescribed in “System Clock andClock Options”onpage 31. If the
level issampled twice by the Watchdog Oscillatorclock but disappears beforetheend
of the start-up time, the MCU will still wakeup, but no interrupt will begenerated.The
requiredlevel must be held long enoughfor the MCU to complete the wakeup to trigger
the level interrupt.
MCU Control Register –
MCUCR
The MCU Control Registercontainscontrolbitsfor interrupt sense control and general
MCU functions.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The ExternalInterrupt1is activatedbytheexternalpin INT1 if the SREG I-bit and the
corresponding interruptmask in the GICRare set. The level and edges on theexternal
INT1 pin that activate theinterruptare defined in Table40.Thevalue on the INT1 pin is
sampledbefore detecting edges. If edge or toggleinterruptisselected, pulses that last
longer than one clock periodwill generate an interrupt. Shorterpulses are not guaran-
teed to generate an interrupt. If lowlevel interruptisselected, the lowlevel must be held
until the completion of the currently executing instruction to generateaninterrupt.
Bit 76543 210
SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 40. Interrupt1Sense Control
ISC11 ISC10 Description
00The lowlevel ofINT1 generates an interrupt request.
01Anylogicalchange on INT1 generates an interrupt request.
10The falling edge ofINT1 generates an interrupt request.
11The rising edge ofINT1 generates an interrupt request.
(24 Seiten)
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