Rainbow-electronics ATmega8515L Bedienungsanleitung Seite 48

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48
ATmega8515(L)
2512A–AVR–04/02
Figure 27. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
Bits 7..5 – Res: Reserved Bits
These bits are reservedbits in the ATmega8515 andwill always read aszero.
Bit 4 WDCE: Watchdog Change Enable
Thisbit must be set when the WDE bit iswritten to logiczero. Otherwise, the Watchdog
will not be disabled. Once writtentoone,hardware will clear thisbit afterfourclock
cycles.Refer to the description of the WDE bit for a Watchdog disable procedure. In
SafetyLevels 1and 2, thisbit mustalso be set when changing the prescalerbits. See
“TimedSequencesforChanging the Configuration of the Watchdog Timer”onpage 50.
Bit 3 – WDE: Watchdog Enable
When the WDE iswritten to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logiczero, the Watchdog Timerfunction isdisabled. WDE can only be cleared
if the WDCE bit haslogiclevel one. To disable an enabledWatchdog Timer, the follow-
ing proceduremust be followed:
Table 20. WDT Configuration as a Function of the Fuse Settings ofS8515C and
WDTON.
S8515C WDTON
Safety
Level
WDT
Initial
State
How to Disable
the WDT
How to
Change Time-
out
UnprogrammedUnprogrammed 1 Disabled TimedsequenceTimed
sequence
Unprogrammed Programmed 2 Enabled Always enabled Timed
sequence
ProgrammedUnprogrammed 0 Disabled Timedsequence No restriction
Programmed Programmed 2 Enabled Always enabled Timed
sequence
WATCHDOG
OSCILLATOR
Bit 76543 210
WDCE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value00000000
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