75
ATmega8515(L)
2512A–AVR–04/02
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The ExternalInterrupt0is activatedbytheexternalpin INT0 if the SREG I-flag and the
corresponding interruptmask are set. The level and edges on theexternalINT0 pin that
activate theinterruptare defined in Table 41. Thevalue on the INT0 pin issampled
before detecting edges. If edge or toggleinterruptisselected, pulses that last longer
than one clock periodwill generateaninterrupt. Shorterpulses are not guaranteed to
generate an interrupt. If lowlevel interruptisselected, the lowlevel must be held until
the completion of the currently executing instruction to generateaninterrupt.
Extended MCU Control
Register – EMCUCR
• Bit 0 – ISC2: Interrupt Sense Control 2
TheAsynchronousExternalInterrupt2is activatedbytheexternalpin INT2 if the SREG
I-bit and the corresponding interruptmask in GICRare set. If ISC2iswritten to zero, a
falling edge on INT2 activates theinterrupt. If ISC2iswrittentoone, a rising edge on
INT2 activates theinterrupt. Edges on INT2 are registered asynchronously.Pulses on
INT2 wider than the minimum pulse width given in Table42will generateaninterrupt.
Shorterpulses are not guaranteed to generateaninterrupt. When changing the ISC2
bit, an interrupt can occur.Therefore, it isrecommended to first disable INT2 by clearing
itsInterrupt Enable bit in the GICRRegister.Then, the ISC2 bit can be changed. Finally,
the INT2 interrupt flag should be clearedbywriting a logical one to itsInterrupt Flag bit
(INTF2) in the GIFR Registerbeforetheinterruptisre-enabled.
General Interrupt Control
Register – GICR
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit isset (one) and the I-bit in the Status Register(SREG) isset (one),
theexternalpin interruptis enabled.The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU GeneralControl Register (MCUCR)define whether the External
Interruptis activated on rising and/orfalling edge of the INT1 pin orlevelsensed.Activity
Table 41. Interrupt0Sense Control
ISC01 ISC00 Description
00The lowlevel ofINT0 generates an interrupt request.
01Anylogicalchange on INT0 generates an interrupt request.
10The falling edge ofINT0 generates an interrupt request.
11The rising edge ofINT0 generates an interrupt request.
Bit 76543 210
SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 42. AsynchronousExternalInterrupt Characteristics
Symbol Parameter Condition Min Typ Max Units
t
INT
Minimum pulse widthfor
asynchronous external interrupt
50 ns
Bit 76543 210
INT1 INT0 INT2
– – – IVSEL IVCE GICR
Read/Write R/W R/W R/W RRRR/W R/W
Initial Value00000000
(24 Seiten)
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