Rainbow-electronics ATmega8515L Bedienungsanleitung PDF herunterladen (Seite 102)

102

ATmega8515(L)

2512A–AVR–04/02

byte iscopied into the highbyte temporary register(TEMP). When the CPUreads the

ICR1HI/Olocation it will access theTEMP Register.

The ICR1 registercan only be written when using a Waveform Generation modethat

utilizes the ICR1 Registerfordefining the counter’s TOPvalue. Inthese cases the

Waveform Generation mode

(WGM13:0)bits must be set beforetheTOPvalue can be

writtentothe ICR1 Register. When writing the ICR1 Register the highbyte must be writ-

tentothe ICR1HI/Olocation beforethe lowbyte iswritten to ICR1L.

For moreinformation on how to access the16-bit registers refer to “Accessing 16-bit

Registers”onpage 97.

Input Capture Trigger Source Themaintriggersource for theinput captureunitis the

Input Capture pin

(ICP1).

Timer/Counter1 can alternatively usetheAnalog Comparator output as triggersource

for theinput captureunit.TheAnalog Comparator isselected as triggersource by set-

ting the

Analog Comparator Input Capture

(ACIC) bit in the

Analog Comparator Control

and Status Register

(ACSR). Beawarethat changing triggersource can trigger a cap-

ture. Theinput capture flag musttherefore be cleared after the change.

Both the

Input Capture pin

(ICP1) and the

Analog Comparator output

(ACO) inputs are

sampled using the same technique asfor theT1pin (Figure44onpage 92).Theedge

detector is alsoidentical. However, when the noise canceler is enabled, additionallogic

is insertedbeforetheedge detector, which increases the delaybyfoursystem clock

cycles. Note that theinput of thenoise canceler and edge detector is always enabled

unless theTimer/Counter isset in a Waveform Generation modethat usesICR1 to

define TOP.

An input capture can betriggeredbysoftware by controlling the portof the ICP1 pin.

Noise Canceler Thenoise canceler improves noise immunitybyusing a simple digitalfiltering scheme.

The noise canceler input is monitored overfoursamples, and all four must beequalfor

changing theoutput that in turnis usedbytheedge detector.

The noise canceler is enabledbysetting the

Input Capture Noise Canceler

(ICNC1)bit

Timer/Counter Control Register B

(TCCR1B). When enabled thenoise canceler intro-

duces additionalfour system clock cycles ofdelayfrom a change applied to theinput, to

theupdate of the ICR1 Register.The noise canceler uses the system clock and is there-

fore not affectedbythe prescaler.

Using the Input Capture Unit Themainchallenge when using theinput capture unit is to assign enoughprocessor

capacityforhandling theincoming events.Thetimebetween two events iscritical. If the

processorhas not read the captured value in the ICR1 Registerbeforethenextevent

occurs, the ICR1 will beoverwritten with anew value. Inthiscasethe resultof the cap-

ture will beincorrect.

When using theinput captureinterrupt, the ICR1 Registershould be read as early in the

interrupt handlerroutine aspossible. Even though theinput captureinterrupt hasrela-

tively highpriority, themaximum interrupt responsetimeisdependent on themaximum

number ofclock cycles it takes to handleany of theother interrupt requests.

Using theinput captureunitinany modeof operation when theTOPvalue (resolution) is

actively changedduring operation, is not recommended.

Measurement of an externalsignal’sduty cycle requires that thetrigger edge ischanged

after each capture. Changing theedge sensing must be done as early aspossibleafter

the ICR1 Registerhasbeen read.After a change of theedge, the Input Capture Flag

(ICF1) must be clearedbysoftware (writing a logical one to the I/Obit location). For

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