
57
ATmega8515(L)
2512A–AVR–04/02
Ports as General Digital
I/O
The ports are bi-directionalI/Oportswith optional internalpull-ups. Figure29shows a
functionaldescription of one I/O-port pin,here generically called Pxn.
Figure 29. GeneralDigitalI/O
(1)
Note: 1. WPx, WDx, RRx, RPx, and RDx are commontoall pinswithin the same port. clk
I/O
,
SLEEP, and PUD are common to all ports.
Configuring the Pin Each port pin consists of three registerbits: DDxn, PORTxn, and PINxn. Asshownin
“RegisterDescription forI/O Ports”onpage 72, the DDxn bits areaccessed at the DDRx
I/O address, thePORTxn bits at thePORTxI/O address, and thePINxn bits at thePINx
I/O address.
The DDxn bit in the DDRx Registerselects the direction of thispin. If DDxniswritten
logic one, Pxnisconfigured as an output pin. If DDxniswritten logiczero, Pxnisconfig-
ured as an input pin.
If PORTxniswritten a logic one when the pin isconfigured as an input pin, the pull-up
resistor is activated.Toswitch the pull-upresistor off, PORTxn has to be written a logic
zeroor the pin has to be configured as an output pin. The port pins aretri-statedwhen a
reset condition becomes active, even if no clocks are running.
If PORTxniswritten a logic one when the pin isconfigured as an output pin, the port pin
isdriven high(one). If PORTxniswritten a logiczero when the pin isconfigured as an
output pin, the port pin isdriven low(zero).
When switching between tri-state ({DDxn, PORTxn}=0b00) and output high({DDxn,
PORTxn}=0b11), an intermediate state with eitherpull-up enabled ({DDxn, PORTxn}=
0b01) or output low({DDxn, PORTxn}=0b10) mustoccur. Normally, the pull-up
clk
RPx
RRx
WPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WPx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clk
I/O
: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
Q
D
Q
Q
D
CLR
PORTxn
Q
Q
D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
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