8
ATmega8515(L)
2512A–AVR–04/02
Status Register The Status Registercontains information about the resultof themost recently executed
arithmetic instruction. This information can beusedfor altering program flow in order to
perform conditional operations. Note that the statusregister is updated after all ALU
operations, asspecified in the Instruction Set Reference. Thiswill in manycases
remove theneedfor using the dedicatedcompareinstructions, resulting in faster and
more compact code.
The statusregister is not automatically storedwhen enteringaninterrupt routine and
restoredwhen returning from an interrupt. This must be handledbysoftware.
TheAVRstatusregister – SREG –isdefined as:
• Bit 7 – I: Global Interrupt Enable
The GlobalInterrupt Enable bit must be set for theinterrupts to be enabled.Theindivid-
ual interrupt enable control is then performed in separate controlregisters. If theglobal
interruptenable register iscleared, none of theinterrupts areenabled independent of
theindividual interrupt enable settings.The I-bit isclearedbyhardwareafter an interrupt
has occurred, and isset by theRETI instruction to enable subsequent interrupts.The I-
bit can also be set andclearedbytheapplication with the SEI andCLIinstructions, as
described in theinstruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructionsBLD(Bit LoaD) andBST (Bit STore) usetheT-bit assourceor
destination for theoperatedbit. A bit from a register in theRegisterFile can be copied
into T by the BSTinstruction, and a bit in T can be copied into a bit in a register in the
RegisterFile by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a half carry in some arithmetic operations. Half Carry is
useful in BCD arithmetic. See the“Instruction Set Description” fordetailed information.
• Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive orbetween the negative flag N and thetwo’scomple-
ment overflowflag V. See the“Instruction Set Description” fordetailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
TheTwo’sComplement OverflowFlag V supports two’scomplement arithmetics. See
the“Instruction Set Description” fordetailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative resultinanarithmetic orlogic operation. See
the“Instruction Set Description” fordetailed information.
•Bit1–Z: Zero Flag
The Zero Flag Z indicates a zero resultinanarithmetic orlogic operation. See the
“Instruction Set Description” fordetailed information.
Bit 76543 210
I THSVNZ CSREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
(24 Seiten)
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