Rainbow-electronics ATmega8515L Bedienungsanleitung PDF herunterladen (Seite 108)

108

ATmega8515(L)

2512A–AVR–04/02

Fast PWM Mode The

fast Pulse Width Modulation

orfastPWM mode (WGM13:0 = 5,6,7,14, or 15)pro-

vides a highfrequency PWM waveformgeneration option. The fastPWM differs from

theother PWM optionsbyitssingle-slopeoperation. The countercountsfrom BOTTOM

to TOPthen restartsfrom BOTTOM. In non-inverting Compare Output mode, the output

compare (OC1x) isset on the comparematch between TCNT1 andOCR1x, andcleared

at TOP. Ininverting Compare Output modeoutput iscleared on comparematch andset

at TOP. Due to the single-slopeoperation, theoperating frequency of the fastPWM

mode can betwiceashigh as the phase correctandphaseandfrequency correctPWM

modes that use dual-slopeoperation. Thishighfrequency makes the fastPWM mode

well suitedforpowerregulation,rectification, andDAC applications. Highfrequency

allows physically small sized externalcomponents(coils, capacitors), hence reduces

totalsystem cost.

ThePWM resolution forfastPWM can be fixed to 8-, 9-, or 10-bit, ordefinedbyeither

ICR1 orOCR1A. The minimum resolution allowed is 2-bit (ICR1 orOCR1A set to

0x0003), and themaximum resolution is 16-bit (ICR1 orOCR1A set to MAX).ThePWM

resolution in bitscan be calculatedbyusing the following equation:

In fastPWM modethe counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5,6,or7),thevalue in

ICR1 (WGM13:0 = 14), or thevalue in OCR1A (WGM13:0 = 15).The counter is then

cleared at the following timerclock cycle. The timing diagram for the fastPWM modeis

showninFigure 52. The figure shows fastPWM mode when OCR1A orICR1 is used to

define TOP. TheTCNT1 value is in the timing diagram shownas a histogram for illus-

trating the single-slopeoperation. The diagram includes non-inverted and inverted PWM

outputs.The small horizontalline marks on theTCNT1 slopesrepresent compare

matchesbetween OCR1x and TCNT1. The OC1x interrupt flag will be set when a com-

parematch occurs.

Figure 52. FastPWM Mode, Timing Diagram

TheTimer/CounterOverflowFlag (TOV1) isset each time the counterreaches TOP. In

addition the OC1A orICF1 flag isset at the same timerclock cycleas TOV1 isset when

FPWM

TOP 1+()log

2()log

-----------------------------------=

TCNTn

1 7

Period

2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx/TOP Update and

TOVn Interrupt Flag Set and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 ... 103 104 105 106 107 108 109 110 111 112 113 ... 222 223

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