12
ATmega8515(L)
2512A–AVR–04/02
also bemoved to the startof the Boot Flash section by programming the BOOTRST
Fuse,see “Boot LoaderSupport–Read-While-Write Self-Programming” on page 162.
When an interruptoccurs, the GlobalInterrupt Enable I-bit iscleared and all interrupts
are disabled.Theusersoftware can write logic one to the I-bit to enablenested inter-
rupts.All enabled interruptscan then interruptthe current interrupt routine. The I-bit is
automatically set whenaReturn from Interruptinstruction – RETI –is executed.
Thereare basically twotypes of interrupts.The firsttypeis triggeredbyan event that
sets theinterrupt flag. For theseinterrupts, theProgram Counter is vectored to the
actualInterruptVector in order to execute theinterrupt handling routine, andhardware
clears the corresponding interrupt flag. Interrupt flagscan also be clearedbywriting a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs whilethe
corresponding Interrupt Enable bit iscleared, theinterrupt flag will be set andremem-
bered until theinterruptis enabled, or the flag isclearedbysoftware. Similarly, if one or
moreinterrupt conditions occurwhilethe GlobalInterrupt Enable bit iscleared, the cor-
responding interrupt flag(s) will be set andremembered until the GlobalInterrupt Enable
bit isset, andwill then beexecutedbyorder ofpriority.
The second typeof interruptswill trigger aslong as theinterrupt condition ispresent.
Theseinterruptsdo not necessarily have interrupt flags. If theinterrupt condition disap-
pears beforetheinterruptis enabled, theinterrupt will not betriggered.
When the AVR exitsfrom an interrupt, it will always returntothemainprogram and exe-
cute one moreinstruction beforeanypending interruptisserved.
Note that the Status Register is not automatically storedwhen enteringaninterrupt rou-
tine, norrestoredwhen returning from an interrupt routine. This must be handledby
software.
When using the CLI instruction to disableinterrupts, theinterruptswill be immediately
disabled. Nointerrupt will beexecuted after the CLI instruction, even if it occurs simulta-
neously with the CLI instruction. The following example shows how thiscan beused to
avoid interruptsduring thetimedEEPROM write sequence..
Assembly Code Example
in r16, SREG
; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE
; start EEPROM write
sbi EECR, EEWE
out SREG, r16
; restore SREG value (I-bit)
CCode Example
char cSREG;
cSREG = SREG;
/* store SREG value */
/*
disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE);
/* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG;
/* restore SREG value (I-bit) */
(24 Seiten)
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